Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER
R01UH0042EJ0500 Rev.5.00 Page 1033 of 1513
Aug 12, 2011
Figure 20-51. Reception via Software Polling
START
END
Read C0RGPT register
Yes
No
ROVF bit = 1?
Yes
No
Clear ROVF bit.
Clear ROVF bit = 1
Clear DN bit.
Clear DN bit = 1
RHPM bit = 1?
No
Yes
CINTS1 bit = 1?
No
Yes
Clear CINTS1 bit.
Clear CINTS1 bit = 1
Read C0MDATAxm,
C0MDLCm, C0MIDLm,
and C0MIDHm registers.
DN bit = 0
AND
MUC bit = 0
Note
Read normal data.
Read illegal data.
Note Check the MUC and DN bits using one read access.
Remarks 1. Check the MBON bit at the start and end of the polling routine to see if the message buffer and
receive history register can be accessed, because a CAN sleep mode transition request which
has been held pending may be under execution. If the MBON bit is cleared (0), stop the
processing under execution. Re-execute the processing after the MBON bit is set (1) again.
2. If the ROVF bit has been once set (1), the receive history list contradicts. Therefore, scan all the
receive message buffers that have completed reception.