Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER
R01UH0042EJ0500 Rev.5.00 Page 1032 of 1513
Aug 12, 2011
Figure 20-50. Reception via Interrupt (Using C0RGPT Register)
END
ROVF bit = 1?
Yes
No
Clear ROVF bit.
Clear ROVF bit = 1
RHPM bit = 1?
Yes
START
No
Clear DN bit.
Clear DN bit = 1
DN bit = 0
AND
MUC bit = 0
Note
Read C0MDATAxm,
C0MDLCm, C0MIDLm,
and C0MIDHm registers.
Yes
No
Receive completion
interrupt
Read C0RGPT register.
Read normal data.
Read illegal data.
Note Check the MUC and DN bits using one read access.
Remarks 1. Check the MBON bit at the start and end of the interrupt routine to see if the message buffer and
receive history register can be accessed, because a CAN sleep mode transition request which
has been held pending may be under execution. If the MBON bit is cleared (0), stop the
processing under execution. Re-execute the processing after the MBON bit is set (1) again. It is
therefore recommended to cancel the CAN sleep mode transition request before executing
reception interrupt servicing.
2. If the ROVF bit has been once set (1), the receive history list contradicts. Therefore, scan all the
receive message buffers that have completed reception.