Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER

R01UH0042EJ0500 Rev.5.00 Page 1031 of 1513

Aug 12, 2011

Figure 20-49. Reception via Interrupt (Using C0LIPT Register)

START

END

Read C0LIPT register.

DN bit = 0

and

MUC bit = 0

Note

Yes

Clear DN bit.

Clear DN bit = 1

Clear CINTS1 bit.

Clear CINTS1 bit = 1

Receive completion

interrupt

Read C0MDATAxm,

C0MDLCm, C0MIDLm, and

C0MIDHm registers.

Note Check the MUC and DN bits using one read access.

Remark Check the MBON bit at the start and end of the interrupt routine to see if the message buffer and

receive history register can be accessed, because a CAN sleep mode transition request which has

been held pending may be under execution. If the MBON bit is cleared (0), stop the processing

under execution. Re-execute the processing after the MBON bit is set (1) again. It is therefore

recommended to cancel the CAN sleep mode transition request before executing reception interrupt

servicing.