Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS
R01UH0042EJ0500 Rev.5.00 Page 103 of 1513
Aug 12, 2011
(1) Port n register (Pn)
Data is input from or output to an external device by writing or reading the Pn register.
The Pn register consists of a port latch that holds output data, and a circuit that reads the status of pins.
Each bit of the Pn register corresponds to one pin of port n, and can be read or written in 1-bit units.
Pn7
Outputs 0.
Outputs 1.
Pnm
0
1
Control of output data (in output mode)
Pn6 Pn5 Pn4 Pn3 Pn2 Pn1 Pn0
01237567
Pn
After reset: 00H (output latch) R/W
Data is written to or read from the Pn register as follows, regardless of the setting of the PMCn register.
Table 4-5. Writing/Reading Pn Register
Setting of PMn Register Writing to Pn Register Reading from Pn Register
Output mode
(PMnm = 0)
Data is written to the output latch
Note
.
In the port mode (PMCn = 0), the contents of the output
latch are output from the pins.
The value of the output latch is read.
Input mode
(PMnm = 1)
Data is written to the output latch.
The pin status is not affected
Note
.
The pin status is read.
Note The value written to the output latch is retained until a new value is written to the output latch.