Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER
R01UH0042EJ0500 Rev.5.00 Page 1026 of 1513
Aug 12, 2011
Figure 20-45. Transmission via Software Polling
START
END
Read C0TGPT register.
CINTS0 bit = 1?
TOVF bit = 1?
Clear TOVF bit.
Clear TOVF bit = 1
THPM bit = 1?
Yes
No
Yes
No
Yes
No
Clear CINTS0 bit.
Clear CINTS0 bit = 1
Clear RDY bit.
Set RDY bit = 0
Clear RDY bit = 1
Set RDY bit.
Set RDY bit = 1
Clear RDY bit = 0
Set TRQ bit.
Set TRQ bit = 1
Clear TRQ bit = 0
RDY bit = 0?
No
Yes
Data frame
or
remote frame?
Set C0MDLCm register.
Set RTR bit of
C0MCONFm register.
Set C0MIDLm and
C0MIDHm registers.
Set C0MDATAxm,
C0MDLCm registers.
Clear RTR bit of
C0MCONFm register.
Set C0MIDLm and
C0MIDHm registers.
Remote frame
Data frame
Cautions 1. The TRQ bit should be set after the RDY bit is set.
2. The RDY bit and TRQ bit should not be set at the same time.
Remarks 1. Check the MBON bit at the start and end of the polling routine to see if the message buffer and
transmit history register can be accessed, because a CAN sleep mode transition request which
has been held pending may be under execution. If the MBON bit is cleared (0), stop the
processing under execution. Re-execute the processing after the MBON bit is set (1) again.
2. If the TOVF bit is set (1) again, the transmit history list contradicts. Therefore, scan all the
transmit message buffers that have completed transmission.