Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER
R01UH0042EJ0500 Rev.5.00 Page 1024 of 1513
Aug 12, 2011
Figure 20-43. Transmission via Interrupt (Using C0LOPT Register)
Start
END
Transmit completion
interrupt servicing
Read C0LOPT register.
Clear RDY bit.
Set RDY bit = 0
Clear RDY bit = 1
RDY bit = 0?
No
Yes
Set RDY bit.
Set RDY bit = 1
Clear RDY bit = 0
Set TRQ bit.
Set TRQ bit = 1
Clear TRQ bit = 0
Data frame
or
remote frame?
Remote frame
Data frame
Set C0MDLCm register.
Set RTR bit of
C0MCONFm register.
Set C0MIDLm and
C0MIDHm registers.
Set C0MDATAxm,
C0MDLCm registers.
Clear RTR bit of
C0MCONFm register.
Set C0MIDLm and
C0MIDHm registers.
Cautions 1. The TRQ bit should be set after the RDY bit is set.
2. The RDY bit and TRQ bit should not be set at the same time.
Remark Check the MBON bit at the start and end of the interrupt routine to see if the message buffer and
transmit history register can be accessed, because a CAN sleep mode transition request which has
been held pending may be under execution. If the MBON bit is cleared (0), stop the processing
under execution. Re-execute the processing after the MBON bit is set (1) again. It is therefore
recommended to cancel the CAN sleep mode transition request before executing transmission
interrupt servicing.