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User’s Manual

All information contained in these materials, including products and product specifications,

represents information on the product at the time of publication and is subject to change by

Renesas Electronics Corp. without notice. Please review the latest information published by

Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.

website (http://www.renesas.com).

V850ES/JG3-H, V850ES/JH3-H

User’s Manual: Hardware

Rev.5.00 Aug, 2011

RENESAS MCU

V850ES/Jx3-H Microcontrollers

www.renesas.com

V850ES/JG3-H V850ES/JH3-H

μPD70F3760 μPD70F3765

μPD70F3761 μPD70F3766

μPD70F3762 μPD70F3767

μPD70F3770 μPD70F3771

Summary of content (1513 pages)

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User’s Manual 32 V850ES/JG3-H, V850ES/JH3-H User’s Manual: Hardware RENESAS MCU V850ES/Jx3-H Microcontrollers V850ES/JG3-H V850ES/JH3-H μPD70F3760 μPD70F3765 μPD70F3761 μPD70F3766 μPD70F3762 μPD70F3767 μPD70F3770 μPD70F3771 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice.
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Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office.
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NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN).
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How to Use This Manual Readers This manual is intended for users who wish to understand the functions of the V850ES/JG3-H and V850ES/JH3-H and design application systems using the V850ES/JG3-H and V850ES/JH3-H. Purpose This manual is intended to give users an understanding of the hardware functions of the V850ES/JG3-H and V850ES/JH3-H shown in the Organization below.
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Conventions Data significance: Higher digits on the left and lower digits on the right Active low representation: xxx (overscore over pin or signal name) Memory map address: Higher addresses on the top and lower addresses on the Note: Footnote for item marked with Note in the text bottom Caution: Information requiring particular attention Remark: Supplementary information Numeric representation: Binary ... xxxx or xxxxB Decimal ... xxxx Hexadecimal ...
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Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850ES/JG3-H and V850ES/JH3-H Document Name Document No. V850ES Architecture User’s Manual U15943E V850ES/JG3-H, V850ES/JH3-H Hardware User’s Manual This manual Documents related to development tools Document Name Document No.
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Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc. EEPROM is a trademark of Renesas Electronics Corporation. IECUBE is a registered trademark of Renesas Electronics Corporation in Japan and Germany. MINICUBE is a registered trademark of Renesas Electronics Corporation in Japan and Germany or a trademark in the United States of America.
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Table of Contents CHAPTER 1 INTRODUCTION................................................................................................................. 19 1.1 General ...................................................................................................................................... 19 1.2 Features .................................................................................................................................... 22 1.3 Application Fields .................................
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4.5.1 4.5.2 4.5.3 4.5.4 4.5.5 4.5.6 Cautions on setting port pins.........................................................................................................172 Cautions on bit manipulation instruction for port n register (Pn)....................................................175 Cautions on on-chip debug pins (V850ES/JG3-H only) ................................................................176 Cautions on P56/INTP05/DRST pin..................................................................
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7.6.1 Free-running timer mode (during timer-tuned operation) ..............................................................311 7.6.2 PWM output mode (during timer-tuned operation) ........................................................................318 7.7 Simultaneous-Start Function ................................................................................................ 320 7.7.1 PWM output mode (simultaneous-start operation) ....................................................................
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.4.1 11.4.2 11.4.3 11.4.4 11.4.5 11.4.6 System outline ..............................................................................................................................591 Dead-time control (generation of negative-phase wave signal).....................................................596 Interrupt culling function ................................................................................................................603 Operation to rewrite register with transfer function............
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16.4.2 Operation in real-time output mode...............................................................................................718 16.4.3 Cautions........................................................................................................................................719 CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) ............................................. 720 17.1 Features .....................................................................................................
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19.1 Mode Switching of I2C Bus and Other Serial Interfaces..................................................... 814 19.1.1 UARTC3 and I2C00 mode switching .............................................................................................814 19.1.2 UARTC4, CSIF0, and I2C01 mode switching ................................................................................815 19.1.3 UARTC1 and I2C02 mode switching ..........................................................................................
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20.3.7 Baud rate control function .............................................................................................................914 20.4 Connection with Target System ........................................................................................... 918 20.5 Internal Registers of CAN Controller ................................................................................... 919 20.5.1 CAN controller configuration ...................................................................
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21.6.2 USB function controller register list .............................................................................................1060 21.6.3 EPC control registers ..................................................................................................................1076 21.6.4 Data hold registers......................................................................................................................1128 21.6.5 EPC request data registers ......................................
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23.6.1 Noise elimination.........................................................................................................................1294 23.6.2 Edge detection ............................................................................................................................1294 23.7 Interrupt Acknowledge Time of CPU.................................................................................. 1302 23.8 Periods in Which Interrupts Are Not Acknowledged by CPU .......................
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28.5 RAM Retention Voltage Detection Operation.................................................................... 1346 CHAPTER 29 CRC FUNCTION.......................................................................................................... 1348 29.1 Functions .............................................................................................................................. 1348 29.2 Configuration............................................................................................
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33.4.3 PLL characteristics......................................................................................................................1416 33.4.4 Internal oscillator characteristics .................................................................................................1416 33.5 DC Characteristics ............................................................................................................... 1417 33.5.1 I/O level............................................................
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R01UH0042EJ0500 Rev.5.00 Aug 12, 2011 V850ES/JG3-H, V850ES/JH3-H RENESAS MCU CHAPTER 1 INTRODUCTION The V850ES/JG3-H and V850ES/JH3-H are products in the low-power series of Renesas Electronics’ V850 single-chip microcontrollers designed for real-time control applications. 1.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 1 INTRODUCTION Table 1-1.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 1 INTRODUCTION Table 1-2.
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V850ES/JG3-H, V850ES/JH3-H 1.2 CHAPTER 1 INTRODUCTION Features { Minimum instruction execution time: 20.8 ns (main clock (fXX) = 48 MHz: VDD = 2.85 to 3.6 V) 30.5 μs (subclock (fXT) = 32.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 1 INTRODUCTION Watchdog timer: 1 channel { Real-time output port: 6 bits × 1 channel { Serial interface: Asynchronous serial interface C (UARTC) 3-wire variable-length serial interface F (CSIF) I2C bus interface (I2C) CAN interface USB function interface UARTC/CSIF: 2 channels UARTC/CSIF/I2C: 1 channel UARTC/I2CNote: 2 channels CSIF: 2 channels USB function: 1 channel Note In the μPD70F3770 and 70F3771, one channel is shared with CAN.
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V850ES/JG3-H, V850ES/JH3-H 1.3 CHAPTER 1 INTRODUCTION Application Fields Equipment requiring a USB interface such as home audio systems, printers, and scanners. 1.
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V850ES/JG3-H, V850ES/JH3-H 1.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 1 INTRODUCTION • V850ES/JH3-H 128-pin plastic LQFP (fine pitch) (14 × 20) μPD70F3766GF-GAT-AX μPD70F3767GF-GAT-AX 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 P70/ANI0 P71/ANI1 P72/ANI2 P73/ANI3 P74/ANI4 P75/ANI5 P76/ANI6 P77/ANI7 P78/ANI8 P79/ANI9 P710/ANI10 P711/ANI11 PCS3/CS3 PDL15/AD15 PDL14/AD14 PDL13/AD13 PDL12/AD12 PDL11/AD11 PDL10/AD10 PDL9/AD9 PDL8/AD8 EVDD VSS PDL7/AD7 PDL6/AD6 PDL5/AD5/FLMD1 μPD70
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 1 INTRODUCTION Pin names Address bus A0 to A23: Address/data bus AD0 to AD15: A/D trigger input ADTRG: Analog input ANI0 to ANI11: Analog output ANO0, ANO1: Asynchronous serial clock ASCKC0: Address strobe ASTB: Analog reference voltage AVREF0, AVREF1: Grand for analog pin AVSS: Clock output CLKOUT: CAN receive data CRXD0: Chip select CS0, CS2, CS3: CAN transmit data CTXD0: Debug clock DCK: Debug data input DDI: Debug data output DDO: Debug mode select DMS: Debug reset D
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V850ES/JG3-H, V850ES/JH3-H 1.6 CHAPTER 1 INTRODUCTION Function Block Configuration 1.6.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 1 INTRODUCTION • V850ES/JH3-H Flash memory TIAA00 to TIAA30, TIAA50, TIAA01 to TIAA31, TIAA51, TOAA1OFF TOAA00 to TOAA30, TOAA50, TOAA01 to TOAA31, TOAA51 PC RAM 32-bit barrel shifter Note 2 System register HLDAK 16-bit timer/ counter AB: 2 ch 16-bit timer/ counter AA: 6 ch 16-bit timer/ counter T: 1 ch WDT RTC1HZ RTCCL RTCDIV RTC RTP00 to RTP05 RTO CSIF: 5 ch RXDC0 to RXDC4 TXDC0 to TXDC4 ASCKC0 UARTC: 5 ch SDA00 to SDA02 SCL00 to SCL02 I2C: 3 ch CR
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V850ES/JG3-H, V850ES/JH3-H 1.6.2 CHAPTER 1 INTRODUCTION Internal units (1) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits → 32 bits) and a barrel shifter (32 bits) contribute to faster complex processing.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 1 INTRODUCTION (9) Real-time counter (for watch) The real-time counter counts the reference time (one second) for watch counting based on the subclock (32.768 kHz) or main clock. This can simultaneously be used as the interval timer based on the main clock. Hardware counters dedicated to year, month, day of week, day, hour, minute, and second are provided, and can count up to 99 years.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 1 INTRODUCTION (18) DCU (debug control unit) An on-chip debug function that uses the JTAG (Joint Test Action Group) communication specifications is provided. Switching between the normal port function and on-chip debugging function is done with the control pin input level and the OCDM register. (19) Ports The following general-purpose port functions and control pin functions are available.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 2 PIN FUNCTIONS CHAPTER 2 PIN FUNCTIONS 2.1 List of Pin Functions The names and functions of the pins of the V850ES/JG3-H and V850ES/JH3-H are described below. There are four types of pin I/O buffer power supplies: AVREF0, AVREF1, EVDD, and UVDD. The relationship between these power supplies and the pins is described below. Table 2-1.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 2 PIN FUNCTIONS (1) Port pins (1/4) Pin Name I/O Function Alternate Function Pin No.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 2 PIN FUNCTIONS (2/4) Pin Name I/O Function Alternate Function Pin No. JG3-H JH3-H P60 I/O P61 Port 6 6-bit I/O port Input/output can be specified in 1-bit units.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 2 PIN FUNCTIONS (3/4) Pin Name I/O Function Alternate Function Pin No. JG3-H JH3-H P98 I/O Port 9 16-bit I/O port Input/output can be specified in 1-bit units.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 2 PIN FUNCTIONS (4/4) Pin Name I/O Function Alternate Function Pin No.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 2 PIN FUNCTIONS (2) Non-port Pins (1/9) Pin Name I/O Function Alternate Function Pin No.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 2 PIN FUNCTIONS (2/9) Pin Name I/O Function Alternate Function Pin No.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 2 PIN FUNCTIONS (3/9) Pin Name I/O Function Alternate Function Pin No.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 2 PIN FUNCTIONS (4/9) Pin Name I/O Function Alternate Function Pin No. JG3-H JH3-H Key interrupt input.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 2 PIN FUNCTIONS (5/9) Pin Name I/O Function Alternate Function Pin No.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 2 PIN FUNCTIONS (6/9) Pin Name I/O Function Alternate Function Pin No. JG3-H JH3-H TECR0 Input TENC00 TMT0 encoder clear input TMT0 encoder input TENC01 TIAA00 Input External event count input/capture trigger P93/TIT00/TOT00 45 − P93/TIT00/TOT00/A3 − 57 P94/TIAA31/TOAA31/EVTT0 46 − P94/TIAA31/TOAA31/EVTT0/A4 − 58 P92/TIT01/TOT01 44 − P92/TIT01/TOT01/A2 − 56 P32/ASCKC0/SCKF4/TOAA00 27 39 input/external trigger input (TAA0).
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 2 PIN FUNCTIONS (7/9) Pin Name I/O Function Alternate Function Pin No. JG3-H JH3-H TIT00 Input TIT01 Input Output TOAA00 TOAA01 P93/TECR0/TOT00 45 − P93/TECR0/TOT00/A3 − 57 P92/TENC01/TOT01 44 − P92/TENC01/TOT01/A2 − 56 Timer output (TAA0) P32/ASCKC0/SCKF4/TIAA00 27 39 N-ch open-drain output selectable P33/TIAA01/RTCDIV/RTCCL 28 40 TMT0 external trigger input/capture trigger input TMT0 capture trigger input 5 V tolerant.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 2 PIN FUNCTIONS (8/9) Pin Name I/O Function Alternate Function Pin No.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 2 PIN FUNCTIONS (9/9) Pin Name I/O Function Alternate Function Pin No.
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V850ES/JG3-H, V850ES/JH3-H 2.2 CHAPTER 2 PIN FUNCTIONS Pin States The operation states of pins in the various operation modes are described below. Table 2-2.
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V850ES/JG3-H, V850ES/JH3-H 2.3 CHAPTER 2 PIN FUNCTIONS Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins Table 2-3. Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins (1/4) Pin Alternate Function P00 P01 I/O Circuit Recommended Connection JG3-H JH3-H Type Name 10-D INTP00 Input: INTP01 Independently connect to EVDD or VSS − √ via a resistor. − √ √ √ Output: Leave open.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 2 PIN FUNCTIONS Table 2-3. Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins (2/4) Pin Name P60 Alternate Function TOAB1T1/TIAB11/TOAB11/WAIT I/O Circuit Type 10-D P62 P63 P64 P65 Input: Independently connect to EVDD or VSS via a resistor. Output: Leave open.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 2 PIN FUNCTIONS Table 2-3. Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins (3/4) Pin Alternate Function Name P913 I/O Circuit Recommended Connection Independently connect to EVDD or VSS √ − via a resistor. − √ TIAA51/TOAA51/INTP17 √ − TIAA51/TOAA51/INTP17/A14 − √ TIAA50/TOAA50/INTP18 √ − TIAA50/TOAA50/INTP18/A15 − √ Independently connect to EVDD or VSS − √ via a resistor.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 2 PIN FUNCTIONS Table 2-3. Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins (4/4) Pin Alternate Function Name I/O Circuit Recommended Connection JG3-H JH3-H Type REGC − − Connect to regulator output stabilization capacitor. √ √ RESET − 2 − √ √ UDMF − − Always directly connect to ground via a resistor. √ √ UDPF − − Always directly connect to ground. (The same √ √ √ √ √ √ √ √ applies during standby.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 2 PIN FUNCTIONS Figure 2-1.
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V850ES/JG3-H, V850ES/JH3-H 2.4 CHAPTER 2 PIN FUNCTIONS Cautions When the power is turned on, the following pins may output an undefined level temporarily even during reset. • P10/ANO0 pin • P11/ANO1 pin • DDO pin (V850ES/JH3-H only) • P53/SIF2/TIAB00/KR3/TOAB00/RTP03/DDO pin (V850ES/JG3-H only) R01UH0042EJ0500 Rev.5.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 3 CPU FUNCTION CHAPTER 3 CPU FUNCTION The CPU of the V850ES/JG3-H and V850ES/JH3-H is based on RISC architecture and executes almost all instructions with one clock by using a 5-stage pipeline. 3.1 Features Minimum instruction execution time: 20.8 ns (operating with main clock (fXX) of 48 MHz: VDD = 2.85 to 3.6 V) 30.5 μs (operating with subclock (fXT) of 32.
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V850ES/JG3-H, V850ES/JH3-H 3.2 CHAPTER 3 CPU FUNCTION CPU Register Set The registers of the V850ES/JG3-H and V850ES/JH3-H can be classified into two types: general-purpose program registers and dedicated system registers. All the registers are 32 bits wide. For details, refer to the V850ES Architecture User’s Manual.
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V850ES/JG3-H, V850ES/JH3-H 3.2.1 CHAPTER 3 CPU FUNCTION Program register set The program registers include general-purpose registers and a program counter. (1) General-purpose registers (r0 to r31) Thirty-two general-purpose registers, r0 to r31, are available. Any of these registers can be used to store a data variable or an address variable. However, r0 and r30 are implicitly used by instructions and care must be exercised when these registers are used.
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V850ES/JG3-H, V850ES/JH3-H 3.2.2 CHAPTER 3 CPU FUNCTION System register set The system registers control the status of the CPU and hold interrupt information. These registers can be read or written by using system register load/store instructions (LDSR and STSR), using the system register numbers listed below. Table 3-2.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 3 CPU FUNCTION (1) Interrupt status saving registers (EIPC and EIPSW) EIPC and EIPSW are used to save the status when an interrupt occurs. If a software exception or a maskable interrupt occurs, the contents of the program counter (PC) are saved to EIPC, and the contents of the program status word (PSW) are saved to EIPSW (these contents are saved to the NMI status saving registers (FEPC and FEPSW) if a non-maskable interrupt occurs).
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 3 CPU FUNCTION (2) NMI status saving registers (FEPC and FEPSW) FEPC and FEPSW are used to save the status when a non-maskable interrupt (NMI) occurs. If an NMI occurs, the contents of the program counter (PC) are saved to FEPC, and those of the program status word (PSW) are saved to FEPSW. The address of the instruction next to the one of the instruction under execution, except some instructions, is saved to FEPC when an NMI occurs.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 3 CPU FUNCTION (4) Program status word (PSW) The program status word (PSW) is a collection of flags that indicate the status of the program (result of instruction execution) and the status of the CPU. If the contents of a bit of this register are changed by using the LDSR instruction, the new contents are validated immediately after completion of LDSR instruction execution.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 3 CPU FUNCTION (2/2) Note The result of the operation that has performed saturation processing is determined by the contents of the OV and S flags. The SAT flag is set to 1 only when the OV flag is set to 1 when a saturation operation is performed.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 3 CPU FUNCTION (6) Exception/debug trap status saving registers (DBPC and DBPSW) DBPC and DBPSW are exception/debug trap status registers. If an exception trap or debug trap occurs, the contents of the program counter (PC) are saved to DBPC, and those of the program status word (PSW) are saved to DBPSW. The contents to be saved to DBPC are the address of the instruction next to the one that is being executed when an exception trap or debug trap occurs.
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V850ES/JG3-H, V850ES/JH3-H 3.3 CHAPTER 3 CPU FUNCTION Operation Modes The V850ES/JG3-H and V850ES/JH3-H have the following operation modes. (1) Normal operation mode In this mode, each pin related to the bus interface is set to the port mode after system reset has been released. Execution branches to the reset entry address of the internal ROM, and then instruction processing is started.
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V850ES/JG3-H, V850ES/JH3-H 3.4 3.4.1 CHAPTER 3 CPU FUNCTION Address Space CPU address space For instruction addressing, up to a combined total of 16 MB of external memory area and internal ROM area, plus an internal RAM area, are supported in a linear address space (program space) of up to 64 MB. For operand addressing (data access), up to 4 GB of a linear address space (data space) is supported. The 4 GB address space, however, is viewed as 64 images of a 64 MB physical address space.
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V850ES/JG3-H, V850ES/JH3-H 3.4.2 CHAPTER 3 CPU FUNCTION Wraparound of CPU address space (1) Program space Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. The higher 6 bits ignore a carry or borrow from bit 25 to 26 during branch address calculation. Therefore, the highest address of the program space, 03FFFFFFH, and the lowest address, 00000000H, are contiguous addresses.
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V850ES/JG3-H, V850ES/JH3-H 3.4.3 CHAPTER 3 CPU FUNCTION Memory map The areas shown below are reserved in the V850ES/JG3-H and V850ES/JH3-H. Figure 3-2.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 3 CPU FUNCTION Figure 3-3. Program Memory Map 03FFFFFFH 03FFF000H 03FFEFFFH Use prohibited (program fetch prohibited area) Internal RAM area (60 KB) 03FF0000H 03FEFFFFH Use prohibited (program fetch prohibited area) 01000000H 00FFFFFFH External memory area (14 MB) 00200000H 001FFFFFH 00100000H 000FFFFFH 00000000H R01UH0042EJ0500 Rev.5.
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V850ES/JG3-H, V850ES/JH3-H 3.4.4 CHAPTER 3 CPU FUNCTION Areas (1) Internal ROM area Up to 1 MB is reserved as an internal ROM area. (a) Internal ROM (256 KB) 256 KB are allocated to addresses 00000000H to 0003FFFFH in the following products. Accessing addresses 00040000H to 000FFFFFH is prohibited. • μPD70F3760, 70F3770, 70F3765, 70F3771 Figure 3-4.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 3 CPU FUNCTION (c) Internal ROM (512 KB) 512 KB are allocated to addresses 00000000H to 0007FFFFH in the following products. Accessing addresses 00080000H to 000FFFFFH is prohibited. • μPD70F3762, 70F3767 Figure 3-6. Internal ROM Area (512 KB) 000FFFFFH Access-prohibited area 00080000H 0007FFFFH Internal ROM (512 KB) 00000000H R01UH0042EJ0500 Rev.5.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 3 CPU FUNCTION (2) Internal RAM area Up to 60 KB are reserved as the internal RAM area. The V850ES/JG3-H and V850ES/JH3-H include a data-only RAM of 8 KB in addition to the internal RAM. The RAM capacity of V850ES/JG3-H and V850ES/JH3-H is as follows.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 3 CPU FUNCTION (b) Internal RAM (40 KB) 40 KB are allocated to addresses 03FF5000H to 03FFEFFFH in the following products. Accessing addresses 03FF0000H to 03FF4FFFH is prohibited. • μPD70F3761, 70F3766 Figure 3-8.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 3 CPU FUNCTION (d) Data-only RAM (8 KB) A data-only RAM of 8 KB is allocated to addresses 00280000H to 00281FFFH in the V850ES/JG3-H and V850ES/JH3-H. Figure 3-10. Data-Only RAM Area (8 KB) Logical address space Access-prohibited area 00282000H 00281FFFH Data-only RAM (8 KB) Access-prohibited area Caution 00280000H 0027FFFFH If using the data-only RAM area, the following two register setting are needed.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 3 CPU FUNCTION (3) On-chip peripheral I/O area 4 KB of addresses 03FFF000H to 03FFFFFFH are reserved as the on-chip peripheral I/O area. Figure 3-11.
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V850ES/JG3-H, V850ES/JH3-H 3.4.5 CHAPTER 3 CPU FUNCTION Recommended use of address space The architecture of the V850ES/JG3-H and V850ES/JH3-H requires that a register that serves as a pointer be secured for address generation when operand data in the data space is accessed. The address stored in this pointer ±32 KB can be directly accessed by an instruction for operand data.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 3 CPU FUNCTION (2) Data space With the V850ES/JG3-H and V850ES/JH3-H, it seems that there are sixty-four 64 MB address spaces on the 4 GB CPU address space. Therefore, the least significant bit (bit 25) of a 26-bit address is sign-extended to 32 bits and allocated as an address. (a) Application example of wraparound If R = r0 (zero register) is specified for the LD/ST disp16 [R] instruction, a range of addresses 00000000H ±32 KB can be addressed by sign-extended disp16.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 3 CPU FUNCTION Figure 3-12.
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V850ES/JG3-H, V850ES/JH3-H 3.4.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 3 CPU FUNCTION (2/14) Address Function Register Name Symbol R/W Manipulatable Bits Default Value 1 8 16 √ Undefined DBC0 √ Undefined DBC1 √ Undefined DBC2 √ Undefined DMA transfer count register 3 DBC3 √ Undefined DMA addressing control register 0 DADC0 √ 0000H FFFFF0D2H DMA addressing control register 1 DADC1 √ 0000H FFFFF0D4H DMA addressing control register 2 DADC2 √ 0000H FFFFF0D6H DMA addressing control register 3 DADC3 √ 0000H
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 3 CPU FUNCTION (3/14) Address Function Register Name Symbol R/W Manipulatable Bits Default Value 1 8 √ √ 47H PIC11 √ √ 47H Interrupt control register PIC12 √ √ 47H FFFFF12CH Interrupt control register PIC13 √ √ 47H FFFFF12EH Interrupt control register PIC14 √ √ 47H FFFFF130H Interrupt control register PIC15 √ √ 47H FFFFF132H Interrupt control register PIC16 √ √ 47H FFFFF134H Interrupt control register PIC17 √ √ 47H FFFFF136
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 3 CPU FUNCTION (4/14) Address Function Register Name Symbol R/W R/W Manipulatable Bits Default Value 1 8 √ √ 47H TM3EQIC0 √ √ 47H CF0RIC/IICIC1 √ √ 47H Interrupt control register CF0TIC √ √ 47H Interrupt control register CF1RIC √ √ 47H Interrupt control register CF1TIC √ √ 47H FFFFF17CH Interrupt control register TM2EQIC0 FFFFF17EH Interrupt control register FFFFF180H Interrupt control register FFFFF182H FFFFF184H FFFFF186H 16 FF
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 3 CPU FUNCTION (5/14) Address Function Register Name Symbol R/W Manipulatable Bits Default Value 1 8 16 √ √ 00H FFFFF202H A/D converter channel specification register ADA0S FFFFF203H A/D converter mode register 2 ADA0M2 √ √ 00H FFFFF204H Power-fail compare mode register ADA0PFM √ √ 00H FFFFF205H Power-fail compare threshold value register ADA0PFT √ √ FFFFF210H A/D conversion result register 0 ADA0CR0 A/D conversion result register 0H ADA0
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 3 CPU FUNCTION (6/14) Address Function Register Name Symbol R/W Manipulatable Bits Default Value 1 8 16 √ √ 00H √ √ 00H √ √ 00H Note 1 FFFFF400H Port 0 register P0 FFFFF402H Port 1 register P1 FFFFF404H Port 2 register FFFFF406H Port 3 register P3 √ √ 00H FFFFF408H Port 4 register P4 √ √ 00H FFFFF40AH Port 5 register P5 √ √ 00H FFFFF40CH Port 6 register P6 √ √ 00H FFFFF40EH Port 7 register L P7L √ √ 00H FFFFF40FH Por
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 3 CPU FUNCTION (7/14) Address Function Register Name Symbol R/W Manipulatable Bits Default Value 1 FFFFF472H Port 9 function control register PFC9 8 16 √ R/W 0000H FFFFF472H Port 9 function control register L PFC9L √ √ 00H FFFFF473H Port 9 function control register H PFC9H √ √ 00H Data wait control register 0 DWC0 √ 7777H FFFFF488H Address wait control register AWC √ FFFFH FFFFF48AH Bus cycle control register BCC √ AAAAH FFFFF540H TA
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 3 CPU FUNCTION (8/14) Address Function Register Name Symbol R/W Manipulatable Bits Default Value 1 8 √ √ 00H TT0OPT1 √ √ 00H TMT0 option register 2 TT0OPT2 √ √ TMT0 capture/compare register 0 TT0CCR0 FFFFF607H TMT0 option register 0 TT0OPT0 FFFFF608H TMT0 option register 1 FFFFF609H FFFFF60AH R/W 16 00H √ 0000H FFFFF60CH TMT0 capture/compare register 1 TT0CCR1 √ 0000H FFFFF60EH TMT0 counter read buffer register TT0CNT R √ 0000H FFFF
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 3 CPU FUNCTION (9/14) Address Symbol R/W TAA3 I/O control register 2 TAA3IOC2 R/W FFFFF665H TAA3 option register 0 TAA3OPT0 FFFFF666H TAA3 capture/compare register 0 TAA3CCR0 √ 0000H FFFFF668H TAA3 capture/compare register 1 TAA3CCR1 √ 0000H FFFFF66AH TAA3 counter read buffer register TAA3CNT R FFFFF66CH TAA3 I/O control register4 TAA3IOC4 R/W FFFFF670H TAA4 control register 0 FFFFF671H TAA4 control register 1 FFFFF676H TAA4 capture compar
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 3 CPU FUNCTION (10/14) Address Function Register Name Symbol R/W Manipulatable Bits Default Value 1 8 √ √ 00H DTFR0 √ √ 00H DMA trigger factor register 1 DTFR1 √ √ 00H DMA trigger factor register 2 DTFR2 √ √ 00H R/W 16 FFFFF80CH Internal oscillation mode register RCM FFFFF810H DMA trigger factor register 0 FFFFF812H FFFFF814H FFFFF820H Power save mode register PSMR √ √ 00H FFFFF822H Clock control register CKC √ √ 0AH FFFFF824H Lo
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 3 CPU FUNCTION (11/14) Address Function Register Name Symbol FFFFFA24H UARTC2 status register UC2STR FFFFFA26H UARTC2 receive data register UC2RX UARTC2 receive data register L UC2RXL UARTC2 transmit data register UC2TX FFFFFA26H FFFFFA28H R/W Manipulatable Bits Default Value R/W 1 8 √ √ 16 00H √ R √ FFH √ R/W 01FFH 01FFH UARTC2 transmit data register L UC2TXL √ FFH FFFFFA2AH UARTC2 option control register 1 UC2OPT1 √ √ 00H FFFFFA30H
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 3 CPU FUNCTION (12/14) Address Function Register Name Symbol R/W Manipulatable Bits Default Value 1 8 16 √ 00H √ 12H √ 00H √ √ 00H RC1CC1 √ √ 00H RC1CC2 √ √ 00H RC1CC3 √ √ 00H R/W FFFFFADAH Alarm minute set register RC1ALM FFFFFADBH Alarm time set register RC1ALH FFFFFADCH Alarm week set register RC1ALW √ FFFFFADDH RTC control register 0 RC1CC0 FFFFFADEH RTC control register 1 FFFFFADFH RTC control register 2 FFFFFAE0H RTC co
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 3 CPU FUNCTION (13/14) Address Function Register Name Symbol R/W Manipulatable Bits Default Value 1 FFFFFD14H FFFFFD14H FFFFFD16H CSIF1 receive data register CF1RX CSIF1 receive data register L CF1RXL CSIF1 transmit data register CF1TX 8 16 √ R √ 00H √ R/W 0000H 0000H CSIF1 transmit data register L CF1TXL √ 00H FFFFFD20H CSIF2 control register 0 CF2CTL0 √ √ 01H FFFFFD21H CSIF2 control register 1 CF2CTL1 √ √ 00H FFFFFD22H CSIF2 control r
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 3 CPU FUNCTION (14/14) Address FFFFFDA2H Function Register Name Symbol R/W Manipulatable Bits Default Value R/W IIC control register 2 IICC2 FFFFFDA3H Slave address register 2 SVA2 FFFFFDA4H IIC clock select register 2 IICCL2 FFFFFDA5H IIC function expansion register 2 IICX2 FFFFFDA6H IIC status register 2 IICS2 R FFFFFDAAH IIC flag register 2 IICF2 R/W FFFFFF40H USB clock selection register FFFFFF41H USB function control register 8 √ √ 16
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V850ES/JG3-H, V850ES/JH3-H 3.4.7 CHAPTER 3 CPU FUNCTION Programmable peripheral I/O registers The BPC register is used to select the programmable peripheral I/O register area. The BPC register is valid only μPD70F3770, 70F3771. (1) Peripheral I/O area select control register (BPC) This register can be read or written in 16-bit units. Reset sets this register to 0000H.
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V850ES/JG3-H, V850ES/JH3-H 3.4.8 CHAPTER 3 CPU FUNCTION Special registers Special registers are registers that are protected from being written with illegal data due to a program loop. The V850ES/JG3-H and V850ES/JH3-H have the following eight special registers.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 3 CPU FUNCTION (1) Setting data to special registers Set data to the special registers in the following sequence. <1> Disable DMA operation. <2> Prepare data to be set to the special register in a general-purpose register. <3> Write the data prepared in <2> to the PRCMD register. <4> Write the setting data to the special register (by using the following instructions).
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 3 CPU FUNCTION (2) Command register (PRCMD) The PRCMD register is an 8-bit register that protects the registers that may seriously affect the application system from being written, so that the system does not inadvertently stop due to a program hang-up. The first write access to a special register is valid after data has been written in advance to the PRCMD register.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 3 CPU FUNCTION (3) System status register (SYS) Status flags that indicate the operation status of the overall system are allocated to this register. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
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V850ES/JG3-H, V850ES/JH3-H 3.4.9 CHAPTER 3 CPU FUNCTION Cautions (1) Registers to be set first Be sure to set the following registers first when using the V850ES/JG3-H and V850ES/JH3-H. • System wait control register (VSWC) • On-chip debug mode register (OCDM) (V850ES/JG3-H only) • Watchdog timer mode register 2 (WDTM2) After setting the VSWC, OCDM, and WDTM2 registers, set the other registers as necessary.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 3 CPU FUNCTION (2) Accessing specific on-chip peripheral I/O registers This product has two types of internal system buses. One is a CPU bus and the other is a peripheral bus that interfaces with low-speed peripheral hardware. The clock of the CPU bus and the clock of the peripheral bus are asynchronous. If an access to the CPU and an access to the peripheral hardware conflict, therefore, unexpected illegal data may be transferred.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 3 CPU FUNCTION (2/2) Peripheral Function 2 2 Register Name Access k I C00 to I C02 IICS0 to IICS2 Read 1 CRC CRCD Write 1 CAN controller C0GMABT, Read/Write fXX/fCANMOD + 1) / (2 + j) (MIN.) (m = 0 to 31, a = 1 to 4) C0GMABTD, Note Note (2 × fXX/fCANMOD + 1) / (2 + j) (MAX.) C0MASKaL, C0MASKaH, C0LEC, C0INFO, C0ERC, C0IE, C0INTS, C0BRP, C0BTR, C0TS C0GMCTRL, Read/Write C0GMCS, Note (fXX/fCAN + 1) / (2 + j) (MIN.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 3 CPU FUNCTION (3) Restriction on conflict between sld instruction and interrupt request (a) Description If a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an interrupt request before the instruction in <1> is complete, the execution result of the instruction in <1> may not be stored in a register. Instruction <1> • ld instruction: ld.b, ld.h, ld.w, ld.bu, ld.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS CHAPTER 4 PORT FUNCTIONS 4.1 Features { I/O ports • V850ES/JG3-H: 77 5 V tolerant/N-ch open-drain output selectable: 22 • V850ES/JH3-H: 96 5 V tolerant/N-ch open-drain output selectable: 25 { Input/output specifiable in 1-bit units 4.2 Basic Port Configuration The V850ES/JG3-H features a total of 77 I/O ports consisting of ports 0, 1, 3 to 7, 9, CM, CT, and DL.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS Figure 4-1. Port Configuration Diagram (V850ES/JG3-H) Port 0 P02 P03 P04 P05 P10 Port 1 P11 P60 Port 6 P65 P70 Port 7 P711 P90 P30 Port 3 Port 9 P915 P37 PCM1 Port CM P42 PCT0 PCT1 Port CT P50 PDL0 P56 PDL15 P40 Port 4 Port DL Port 5 Caution Ports 0, 3 to 5 are 5 V tolerant. Figure 4-2.
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V850ES/JG3-H, V850ES/JH3-H 4.3 CHAPTER 4 PORT FUNCTIONS Port Configuration Table 4-3. Port Configuration (V850ES/JG3-H) Item Configuration Control register Port n mode register (PMn: n = 0, 1, 3 to 7, 9, CM, CT, DL) Port n mode control register (PMCn: n = 0, 3 to 5, 9, CM, CT, DL) Port n function control register (PFCn: n = 0, 3 to 6, 9) Port n function control expansion register (PFCEn: n = 4 to 6, 9) Port n function register (PFn: n = 0, 3 to 5, 9) Ports I/O: 77 Table 4-4.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS (1) Port n register (Pn) Data is input from or output to an external device by writing or reading the Pn register. The Pn register consists of a port latch that holds output data, and a circuit that reads the status of pins. Each bit of the Pn register corresponds to one pin of port n, and can be read or written in 1-bit units.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS (2) Port n mode register (PMn) The PMn register specifies the input or output mode of the corresponding port pin. Each bit of this register corresponds to one pin of port n, and the input or output mode can be specified in 1-bit units.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS (4) Port n function control register (PFCn) The PFCn register specifies the alternate function of a port pin to be used if the pin has two alternate functions. Each bit of this register corresponds to one pin of port n, and the alternate function of a port pin can be specified in 1-bit units.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS (6) Port n function register (PFn) The PFn register specifies normal output or N-ch open-drain output. Each bit of this register corresponds to one pin of port n, and the output mode of the port pin can be specified in 1bit units.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS (7) Port setting Set a port as illustrated below. Figure 4-3.
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V850ES/JG3-H, V850ES/JH3-H 4.3.1 CHAPTER 4 PORT FUNCTIONS Port 0 Port 0 is 4-bit (V850ES/JG3-H)/6-bit (V850ES/JH3-H) port for which I/O settings can be controlled in 1-bit units. Port 0 includes the following alternate-function pins. Table 4-6. Port 0 Alternate-Function Pins Pin Name Pin No.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS (2) Port 0 mode register (PM0) (a) V850ES/JG3-H After reset: FFH PM0 R/W Address: FFFFF420H 7 6 5 4 3 2 1 0 1 1 PM05 PM04 PM03 PM02 1 1 PM0n I/O mode control (n = 2 to 5) 0 Output mode 1 Input mode (b) V850ES/JH3-H After reset: FFH PM0 R/W Address: FFFFF420H 7 6 5 4 3 2 1 0 1 1 PM05 PM04 PM03 PM02 PM01 PM00 PM0n I/O mode control (n = 0 to 5) 0 Output mode 1 Input mode R01UH0042EJ0500 Rev.5.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS (3) Port 0 mode control register (PMC0) (1/2) (a) V850ES/JG3-H After reset: 00H PMC0 R/W Address: FFFFF440H 7 6 5 4 3 2 1 0 0 0 PMC05 PMC04 PMC03 PMC02 0 0 PMC05 Specification of P05 pin operation mode 0 I/O port 1 INTP04 input PMC04 Specification of P04 pin operation mode 0 I/O port 1 INTP03 input PMC03 Specification of P03 pin operation mode 0 I/O port 1 INTP02 input/ADTRG input/UCLK input PMC02 Specification of P
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS (2/2) (b) V850ES/JH3-H After reset: 00H PMC0 R/W Address: FFFFF440H 7 6 5 4 3 2 1 0 0 0 PMC05 PMC04 PMC03 PMC02 PMC01 PMC00 PMC05 Specification of P05 pin operation mode 0 I/O port 1 INTP04 input PMC04 Specification of P04 pin operation mode 0 I/O port 1 INTP03 input PMC03 Specification of P03 pin operation mode 0 I/O port 1 INTP02 input/ADTRG input/UCLK input PMC02 Specification of P02 pin operation mode 0 I/O po
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS (5) Port 0 function control expansion register (PFCE0) After reset: 00H PFCE0 Remark R/W Address: FFFFF700H 7 6 5 4 3 2 1 0 0 0 0 0 PFCE03 0 0 0 For details of alternate function specification, see 4.3.1 (6) Port 0 alternate function specifications.
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V850ES/JG3-H, V850ES/JH3-H 4.3.2 CHAPTER 4 PORT FUNCTIONS Port 1 Port 1 is a 2-bit port for which I/O settings can be controlled in 1-bit units. Port 1 includes the following alternate-function pins. Table 4-7. Port 1 Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name V850ES/ V850ES/ JG3-H JH3-H I/O P10 3 3 ANO0 Output P11 4 4 ANO1 Output Caution Remark − When the power is turned on, the P10 and P11 pins may output an undefined level temporarily even during reset.
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V850ES/JG3-H, V850ES/JH3-H 4.3.3 CHAPTER 4 PORT FUNCTIONS Port 2 (V850ES/JH3-H only) Port 2 is a 6-bit port for which I/O settings can be controlled in 1-bit units. Port 2 includes the following alternate-function pins. Table 4-8. Port 2 Alternate-Function Pins Pin Name Pin No.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS (3) Port 2 mode control register (PMC2) After reset: 00H PMC2 R/W Address: FFFFF444H 7 6 5 4 3 2 1 0 0 0 PMC25 PMC24 PMC23 PMC22 PMC21 PMC20 PMC25 Specification of P25 pin operation mode 0 I/O port 1 INTP06 input PMC24 Specification of P24 pin operation mode 0 I/O port 1 INTP05 input PMC23 Specification of P23 pin operation mode 0 I/O port 1 SCKF2 I/O/KR5 input/RTP05 output PMC22 Specification of P22 pin operation
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS (5) Port 2 function control expansion register (PFCE2) After reset: 00H PFCE2 Remark R/W Address: FFFFF704H 7 6 5 4 3 0 0 0 0 PFCE23 2 1 0 PFCE22 PFCE21 PFCE20 For details of alternate function specification, see 4.3.3 (6) Port 2 alternate function specifications.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS (7) Port 2 function register (PF2) After reset: 00H PF2 R/W Address: FFFFFC64H 7 6 5 4 3 2 1 0 0 0 PF25 PF24 PF23 PF22 PF21 PF20 PF2n Control of normal output or N-ch open-drain output (n = 0 to 5) 0 Normal output 1 N-ch open-drain output R01UH0042EJ0500 Rev.5.
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V850ES/JG3-H, V850ES/JH3-H 4.3.4 CHAPTER 4 PORT FUNCTIONS Port 3 Port 3 is a 10-bit port that controls I/O in 1-bit units. Port 3 includes the following alternate-function pins. Table 4-9. Port 3 Alternate-Function Pins Pin Name Pin No.
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V850ES/JG3-H, V850ES/JH3-H After reset: 00H PMC3 PMC37 CHAPTER 4 PORT FUNCTIONS R/W PMC36 PMC37 Address: FFFFF446H PMC35 PMC34 PMC33 PMC32 PMC31 PMC30 Specification of P37 pin operation mode 0 I/O port 1 RXDC3 input/SDA00 I/O/CRXD inputNote/UDMAAK0 output PMC36 Specification of P36 pin operation mode 0 I/O port 1 TXDC3 output/SCL00 I/O/CTXD0 outputNote/UDMARQ0 input PMC35 Specification of P35 pin operation mode 0 I/O port 1 TIAA11 input/TOAA11 output/RTC1HZ output PMC34 Spec
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS (4) Port 3 function control register (PFC3) After reset: 00H PFC3 Remark PFC37 R/W Address: FFFFF466H PFC36 PFC35 PFC34 PFC33 PFC32 PFC31 PFC30 For details of alternate function specification, see 4.3.4 (6) Port 3 alternate function specifications.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS PFCE34 PFC34 Specification of P34 pin alternate function 0 0 TIAA10 input 0 1 TOAA10 output 1 0 TOAA1OFF input/INTP09 input 1 1 Setting prohibited Note Note TOAA1OFF and INTP09 are alternate functions. When using the pin as the TOAA1OFF pin, disable INTP09 pin edge detection, which is the alternate function. Also, when using the pin as the INTP09 pin, stop the high-impedance output controller.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS (7) Port 3 function register (PF3) After reset: 00H PF3 PF37 PF3n R/W Address: PF36 PF35 FFFFFC66H PF34 PF32 PF31 PF30 Control of normal output or N-ch open-drain output (n = 0 to 7) 0 Normal output (CMOS output) 1 N-ch open-drain output R01UH0042EJ0500 Rev.5.
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V850ES/JG3-H, V850ES/JH3-H 4.3.5 CHAPTER 4 PORT FUNCTIONS Port 4 Port 4 is a 3-bit port that controls I/O in 1-bit units. Port 4 includes the following alternate-function pins. Table 4-10. Port 4 Alternate-Function Pins Pin Name Pin No.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS (3) Port 4 mode control register (PMC4) After reset: 00H PMC4 0 R/W Address: FFFFF448H 0 0 PMC42 0 0 PMC42 PMC41 PMC40 Specification of P42 pin operation mode 0 I/O port 1 SCKF0 I/O/INTP10 input PMC41 Specification of P41 pin operation mode 0 I/O port 1 SOF0 output/RXDC4 input/SCL01 I/O PMC40 Specification of P40 pin operation mode 0 I/O port 1 SIF0 input/TXDC4 output/SDA01 I/O (4) Port 4 function control register (PFC4) A
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS (6) Port 4 alternate function specifications PFC42 Specification of P42 pin alternate function 0 SCKF0 I/O 1 INTP10 input PFCE41 PFC41 Specification of P41 pin alternate function 0 0 SOF0 output 0 1 RXDC4 input 1 0 SCL01 I/O 1 1 Setting prohibited PFCE40 PFC40 0 0 SIF0 input 0 1 TXDC4 output 1 0 SDA01 I/O 1 1 Setting prohibited Specification of P40 pin alternate function (7) Port 4 function register (PF4) After reset:
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V850ES/JG3-H, V850ES/JH3-H 4.3.6 CHAPTER 4 PORT FUNCTIONS Port 5 Port 5 is 6-bit (V850ES/JG3-H)/2-bit (V850ES/JH3-H) port that controls I/O in 1-bit units. Port 5 includes the following alternate-function pins. Table 4-11. Port 5 Alternate-Function Pins Pin Name P50 Pin No.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS (1) Port 5 register (P5) (a) V850ES/JG3-H After reset: 00H (output latch) P5 0 P56 P5n R/W P55 Address: FFFFF40AH P54 P53 P52 P51 P50 Output data control (in output mode) (n = 0 to 6) 0 Outputs 0. 1 Outputs 1. (b) V850ES/JH3-H After reset: 00H (output latch) P5 0 0 P5n 0 Address: FFFFF40AH 0 0 0 P51 P50 Output data control (in output mode) (n = 0, 1) 0 Outputs 0. 1 Outputs 1. R01UH0042EJ0500 Rev.5.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS (2) Port 5 mode register (PM5) (a) V850ES/JG3-H After reset: FFH R/W PM5 PM56 1 Address: FFFFF42AH PM55 PM5n PM54 PM53 PM52 PM51 PM50 PM51 PM50 I/O mode control (n = 0 to 6) 0 Output mode 1 Input mode (b) V850ES/JH3-H After reset: FFH PM5 1 R/W Address: FFFFF42AH 1 PM5n 1 1 1 I/O mode control (n = 0, 1) 0 Output mode 1 Input mode R01UH0042EJ0500 Rev.5.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS (3) Port 5 mode control register (PMC5) (a) V850ES/JG3-H After reset: 00H PMC5 0 R/W PMC56 Address: FFFFF44AH PMC55 PMC56 PMC54 PMC53 PMC52 PMC51 PMC50 Specification of P56 pin operation mode 0 I/O port 1 INTP05 input PMC55 Specification of P55 pin operation mode 0 I/O port 1 SCKF2 I/O/KR5 input/RTP05 output PMC54 Specification of P54 pin operation mode 0 I/O port 1 SOF2 output/KR4 input/RTP04 output PMC53 Specification of
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS (4) Port 5 function control register (PFC5) (a) V850ES/JG3-H After reset: 00H PFC5 R/W 0 Address: FFFFF46AH 0 PFC55 PFC54 PFC53 PFC52 PFC51 PFC50 0 0 PFC51 PFC50 (b) V850ES/JH3-H After reset: 00H PFC5 Remark R/W 0 Address: FFFFF46AH 0 0 0 For details of alternate function specification, see 4.3.6 (6) Port 5 alternate function specifications.
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V850ES/JG3-H, V850ES/JH3-H PFCE54 Note 1 PFC54 CHAPTER 4 PORT FUNCTIONS Note 1 Specification of P54 pin alternate function 0 0 SOF2 output 0 1 KR4 input 1 0 RTP04 output 1 1 Setting prohibited PFCE53 Note 1 PFC53 Note 1 Specification of P53 pin alternate function 0 0 SIF2 input 0 1 TIAB00 input/KR3 1 0 TOAB00 output 1 1 RTP03 output PFCE52 Note1 PFC52 Note1 Note 2 0 TIAB03 input/KR2 0 1 TOAB03 output 1 0 RTP02 output 1 1 Setting prohibited PFCE51 PFC51 0
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS (7) Port 5 function register (PF5) (a) V850ES/JG3-H After reset: 00H PF5 0 R/W Address: FFFFFC6AH PF56 PF5n PF55 PF54 PF53 PF52 PF51 PF50 Control of normal output or N-ch open-drain output (n = 0 to 6) 0 Normal output (CMOS output) 1 N-ch open-drain output (b) V850ES/JH3-H After reset: 00H PF5 0 PF5n R/W 0 Address: FFFFFC6AH 0 0 0 PF51 PF50 Control of normal output or N-ch open-drain output (n = 0, 1) 0 Normal output (CMO
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V850ES/JG3-H, V850ES/JH3-H 4.3.7 CHAPTER 4 PORT FUNCTIONS Port 6 Port 6 is a 6-bit port for which I/O settings can be controlled in 1-bit units. Port 6 includes the following alternate-function pins. Table 4-12. Port 6 Alternate-Function Pins Pin Name P60 Pin No.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS (2) Port 6 mode register (PM6) After reset: FFH PM6 1 R/W Address: FFFFF42CH 1 PM65 PM6n PM64 PM63 PM62 PM61 PM60 Output data control (in output mode) (n = 0 to 5) 0 Output mode 1 Input mode (3) Port 6 mode control register (PMC6) After reset: 00H PMC6 0 R/W 0 PMC65 Address: FFFFF44CH PMC65 PMC64 PMC63 PMC62 PMC61 PMC60 Specification of P65 pin operation mode 0 I/O port 1 TOAB1B3 output/EVTAB1 input/CS3 outputNote PM
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS (4) Port 6 function control register (PFC6) After reset: 00H PFC6 Remark 0 R/W Address: FFFFF46CH 0 PFC65 PFC64 PFC63 PFC62 PFC61 PFC60 For details of alternate function specification, see 4.3.7 (6) Port 6 alternate function specifications.
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V850ES/JG3-H, V850ES/JH3-H PFCE63 Note CHAPTER 4 PORT FUNCTIONS PFC63 Specification of P63 pin alternate function 0 0 TOAB1B2 output 0 1 TRGAB1 input 1 0 CS0 output 1 1 Setting prohibited PFCE62 Note Note PFC62 Note Specification of P62 pin alternate function 0 0 TOAB1T2 output/TOAB12 output 0 1 TIAB12 input 1 0 ASTB output 1 1 Setting prohibited PFCE61 PFC61 0 0 TOAB1B1 output 0 1 TIAB10 input 1 0 TOAB10 output 1 1 RD output (V850ES/JG3-H) Note Note Speci
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V850ES/JG3-H, V850ES/JH3-H 4.3.8 CHAPTER 4 PORT FUNCTIONS Port 7 Port 7 is a 12-bit port for which I/O settings can be controlled in 1-bit units. Port 7 includes the following alternate-function pins. Table 4-13. Port 7 Alternate-Function Pins Pin Name Pin No.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS (2) Port 7 mode register H, port 7 mode register L (PM7H, PM7L) After reset: FFH R/W Address: PM7L FFFFF42EH, PM7H FFFFF42FH PM7H 1 1 1 1 PM711 PM710 PM79 PM78 PM7L PM77 PM76 PM75 PM74 PM73 PM72 PM71 PM70 PM7n Caution Remark I/O mode control (n = 0 to 11) 0 Output mode 1 Input mode When using the P7n pin as its alternate function (ANIn pin), set the PM7n bit to 1.
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V850ES/JG3-H, V850ES/JH3-H 4.3.9 CHAPTER 4 PORT FUNCTIONS Port 9 Port 9 is a 16-bit port for which I/O settings can be controlled in 1-bit units. Port 9 includes the following alternate-function pins. Table 4-14. Port 9 Alternate-Function Pins Pin Name P90 P91 P92 Pin No.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS (1) Port 9 register (P9) After reset: 0000H (output latch) R/W Address: P9 FFFFF412H, P9L FFFFF412H, P9H FFFFF413H 15 14 13 12 11 10 9 8 P9 (P9H) P915 P914 P913 P912 P911 P910 P99 P98 (P9L) P97 P96 P95 P94 P93 P92 P91 P90 P9n Output data control (in output mode) (n = 0 to 15) 0 Outputs 0. 1 Outputs 1. Remarks 1. The P9 register can be read or written in 16-bit units.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS (3) Port 9 mode control register (PMC9) (1/2) After reset: 0000H R/W 15 PMC9 (PMC9H) (PMC9L) 14 Address: PMC9 FFFFF452H, PMC9L FFFFF452H, PMC9H FFFFF453H 9 8 PMC915 PMC914 PMC913 PMC912 PMC911 PMC910 PMC99 PMC98 PMC97 PMC91 PMC90 PMC96 PMC915 13 PMC95 12 PMC94 11 PMC93 10 PMC92 Specification of P915 pin operation mode 0 I/O port 1 TIAA50 input/TOAA50 output/INTP18 input/A15 outputNote PMC914 Specification of P914 pin operati
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS (2/2) PMC97 Specification of P97 pin operation mode 0 I/O port 1 SIF1 input/TIAA20 input/TOAA20 output/A7 output PMC96 Note Specification of P96 pin operation mode 0 I/O port 1 TIAA21 input/TOAA21 output/INTP11 input/A6 output PMC95 Note Specification of P95 pin operation mode 0 I/O port 1 TIAA30 input/TOAA30 output/A5 output PMC94 Note Specification of P94 pin operation mode 0 I/O port 1 TIAA31 input/TOAA31 output/TENC00 input/
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS (4) Port 9 function control register (PFC9) Caution When performing separate address bus output (A0 to A15), set the PMC9 register to FFFFH for all 16 bits at once after setting the PFC9 register to the FCDFH and PFCE9 register to CFFFH (V850ES/JH3-H only).
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS (5) Port 9 function control expansion register (PFCE9) Caution When performing separate address bus output (A0 to A15), set the PMC9 register to FFFFH for all 16 bits at once after setting the PFC9 register to FCDFH and the PFCE9 register to CFFFH (V850ES/JH3-H only).
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS (6) Port 9 alternate function specifications PFCE915 PFC915 Specification of P915 pin alternate function 0 0 TIAA50 input 0 1 TOAA50 output 1 0 INTP18 input 1 1 Setting prohibited (V850ES/JG3-H) A15 output (V850ES/JH3-H) PFCE914 PFC914 Specification of P914 pin alternate function 0 0 TIAA51 input 0 1 TOAA51 output 1 0 INTP17 input 1 1 Setting prohibited (V850ES/JG3-H) A14 output (V850ES/JH3-H) PFC913 Note Specification of
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V850ES/JG3-H, V850ES/JH3-H PFCE98 Note CHAPTER 4 PORT FUNCTIONS PFC98 Specification of P98 pin alternate function 0 0 SOF1 output 0 1 INTP12 input 1 0 A8 output 1 1 Setting prohibited PFCE97 PFC97 0 0 SIF1 input 0 1 TIAA20 input 1 0 TOAA20 output 1 1 Setting prohibited (V850ES/JG3-H) Note Note Specification of P97 pin alternate function A7 output (V850ES/JH3-H) PFCE96 PFC96 0 0 Specification of P96 pin alternate function TIAA21 input 0 1 TOAA21 output 1 0 INTP11
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS PFCE92 PFC92 Specification of P92 pin alternate function 0 0 TENC01 input 0 1 TIT01 input 1 0 TOT01 output 1 1 Setting prohibited (V850ES/JG3-H) A2 output (V850ES/JH3-H) PFCE91 PFC91 Specification of P91 pin alternate function 0 0 KR7 input 0 1 RXDC1 input 1 0 SCL02 I/O 1 1 Setting prohibited (V850ES/JG3-H) A1 output (V850ES/JH3-H) PFCE90 PFC90 Specification of P90 pin alternate function 0 0 KR6 input 0 1 TXDC1 outpu
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS (7) Port 9 function register (PF9) After reset: 0000H R/W Address: PF9 FFFFFC72H, PF9L FFFFFC72H 15 14 13 12 11 10 9 8 PF9 0 0 0 0 0 0 0 0 (PF9L) 0 0 0 0 0 0 PF91 PF90 PF9n Caution Control of normal output or N-ch open-drain output (n = 0, 1) 0 Normal output (CMOS output) 1 N-ch open-drain output When output pins P90, P91 are pulled up to EVDD or higher, be sure to set the PF9n bit to 1.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS 4.3.10 Port CM Port CM is 1-bit (V850ES/JG3-H)/4-bit (V850ES/JH3-H) port for which I/O settings can be controlled in 1-bit units. Port CM includes the following alternate-function pins. Table 4-15. Port CM Alternate-Function Pins Pin Name Pin No.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS (2) Port CM mode register (PMCM) (a) V850ES/JG3-H After reset: FFH PMCM 1 R/W Address: FFFFF02CH 1 1 1 PMCM1 1 1 PMCM1 1 PMCM2 PMCM1 PMCM0 I/O mode control 0 Output mode 1 Input mode (b) V850ES/JH3-H After reset: FFH PMCM 1 R/W Address: FFFFF02CH 1 PMCMn 1 PMCM3 I/O mode control (n = 0 to 3) 0 Output mode 1 Input mode R01UH0042EJ0500 Rev.5.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS (3) Port CM mode control register (PMCCM) (a) V850ES/JG3-H After reset: 00H PMCCM 0 R/W Address: FFFFF04CH 0 0 PMCCM1 0 0 0 PMCCM1 0 Specification of PCM1 pin operation mode 0 I/O port 1 CLKOUT output (b) V850ES/JH3-H After reset: 00H PMCCM 0 R/W Address: FFFFF04CH 0 PMCCM3 0 PMCCM3 PMCCM2 PMCCM1 PMCCM0 Specification of PCM3 pin operation mode 0 I/O port 1 HLDRQ input PMCCM2 Specification of PCM2 pin operation mode 0 I
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS 4.3.11 Port CS (V850ES/JH3-H only) Port CS is a 3-bit port for which I/O settings can be controlled in 1-bit units. Port CS includes the following alternate-function pins. Table 4-16. Port CM Alternate-Function Pins Pin Name Pin No.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS (3) Port CS mode control register (PMCCS) After reset: 00H PMCCS 0 R/W Address: FFFFF048H 0 PMCCS3 0 PMCCS3 PMCCS2 0 PMCCS0 Specification of PCS3 pin operation mode 0 I/O port 1 CS3 output PMCCS2 Specification of PCS2 pin operation mode 0 I/O port 1 CS2 output PMCCS0 Specification of PCS0 pin operation mode 0 I/O port 1 CS0 output R01UH0042EJ0500 Rev.5.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS 4.3.12 Port CT Port CT is a 2-bit (V850ES/JG3-H)/4-bit (V850ES/JH3-H) port for which I/O settings can be controlled in 1-bit units. Port CT includes the following alternate-function pins. Table 4-17. Port CT Alternate-Function Pins Pin Name Pin No.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS (2) Port CT mode register (PMCT) (a) V850ES/JG3-H After reset: FFH PMCT 1 R/W Address: FFFFF02AH 1 1 PMCTn 1 1 1 PMCT1 PMCT0 PMCT1 PMCT0 I/O mode control (n = 0, 1) 0 Output mode 1 Input mode (b) V850ES/JH3-H After reset: FFH PMCT 1 R/W Address: FFFFF02AH PMCT6 PMCTn PMCT4 1 1 I/O mode control (n = 0, 1, 4, 6) 0 Output mode 1 Input mode R01UH0042EJ0500 Rev.5.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS (3) Port CT mode control register (PMCCT) (a) V850ES/JG3-H After reset: 00H PMCCT 0 R/W Address: FFFFF04AH 0 0 PMCCT1 0 0 0 PMCCT1 PMCCT0 Specification of PCT1 pin operation mode 0 I/O port 1 WR1 output PMCCT0 Specification of PCT0 pin operation mode 0 I/O port 1 WR0 output (b) V850ES/JH3-H After reset: 00H PMCCT 0 R/W Address: FFFFF04AH PMCCT6 PMCCT6 PMCCT4 0 0 PMCCT1 PMCCT0 Specification of PCT6 pin operation mode 0
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS 4.3.13 Port DH (V850ES/JH3-H only) Port DH is an 8-bit port for which I/O settings can be controlled in 1-bit units. Port DH includes the following alternate-function pins. Table 4-18. Port DH Alternate-Function Pins Pin Name Pin No.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS (1) Port DH register (PDH) After reset: 00H (output latch) PDH PDH7 R/W PDH6 PDH5 PDHn Address: FFFFF006H PDH4 PDH3 PDH2 PDH1 PDH0 Output data control (in output mode) (n = 0 to 7) 0 Outputs 0. 1 Outputs 1.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS 4.3.14 Port DL Port DL is a 16-bit port for which I/O settings can be controlled in 1-bit units. Port DL includes the following alternate-function pins. Table 4-19. Port DL Alternate-Function Pins Pin Name Pin No.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS (1) Port DL register (PDL) After reset: 0000H (output latch) R/W Address: PDL FFFFF004H, PDLL FFFFF004H, PDLH FFFFF005H 15 14 13 12 11 10 9 8 PDL (PDLH) PDL15 PDL14 PDL13 PDL12 PDL11 PDL10 PDL9 PDL8 (PDLL) PDL7 PDL6 PDL5 PDL4 PDL3 PDL2 PDL1 PDL0 PDLn Output data control (in output mode) (n = 0 to 15) 0 Outputs 0. 1 Outputs 1. Remarks 1. The PDL register can be read or written in 16-bit units.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS (3) Port DL mode control register (PMCDL) After reset: 0000H 15 R/W 14 Address: PMCDL FFFFF044H, PMCDLL FFFFF044H, PMCDLH FFFFF045H 13 12 11 10 9 8 PMCDL (PMCDLH) PMCDL15 PMCDL14PMCDL13 PMCDL12 PMCDL11PMCDL10 PMCDL9 PMCDL8 (PMCDLL) PMCDL7 PMCDL6 PMCDL5 PMCDL4 PMCDL3 PMCDL2 PMCDL1 PMCDL0 PMCDLn Specification of PDLn pin operation mode (n = 0 to 15) 0 I/O port 1 ADn I/O (address/data bus I/O) Remarks 1.
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Pin Name Alternate Function Name I/O Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) P00Note 1 INTP00 Input P00 = Setting not required PM00 = Setting not required PMC00 = 1 − − P01Note 1 INTP01 Input P01 = Setting not required PM01 = Setting not required PMC01 = 1 − − P02 NMI Input P02 = Setting not required PM02 = Setting not required PMC02 = 1 − P03 INTP02 Input P
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Pin Name Alternate Function Name P22Note P23Note P24Note I/O Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) SOF2 Output P22 = Setting not required PM22 = Setting not required PMC22= 1 PFCE22 = 0 PFC22 = 0 KR4 Input P22 = Setting not required PM22 = Setting not required PMC22= 1 PFCE22 = 0 PFC22 = 1 RTP04 Output P22 = Setting not required PM22 = Setting not required PMC2
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Pin Name Alternate Function Name P34 I/O P40 P41 PFCnx Bit of Other Bits PFCn Register (Registers) Input P34 = Setting not required PM34 = Setting not required PMC34 = 1 PFCE34 = 0 PFC34 = 0 P34 = Setting not required PM34 = Setting not required PMC34 = 1 PFCE34 = 0 PFC34 = 1 Input P34 = Setting not required PM34 = Setting not required PMC34 = 1 PFCE34 = 1 PFC34 = 0 Input P34 = Setting not required PM34 = Setting not required PMC34 = 1 PFCE34 = 1 PFC34 = 0 TIAA11 Input P35 = S
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Pin Name Alternate Function Name P50 P51 P52Note Note P53 I/O Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) TIAB01 Input P50 = Setting not required PM50 = Setting not required PMC50 = 1 PFCE50 = 0 PFC50 = 0 KRM0 (KRM)= 0 KR0 Input P50 = Setting not required PM50 = Setting not required PMC50 = 1 PFCE50 = 0 PFC50 = 0 TAB0TIG2, TAB0TIG3 (TAB0IOC1) = 0 TOAB01 Output P50
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Pin Name Alternate Function Name P55Note P60 P61 P62 P64 PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits PMn Register PMCn Register PFCEn Register PFCn Register (Registers) I/O P55 = Setting not required PM55 = Setting not required PMC55 = 1 PFCE55 = 0 PFC55 = 0 KR5 Input P55 = Setting not required PM55 = Setting not required PMC55 = 1 PFCE55 = 0 PFC55 = 1 RTP05 Output P55 = Setting not required PM55 = Setting not required PMC55 = 1 PFCE55 = 1 PFC55 = 0 TOAB1
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Pin Name Alternate Function Name I/O Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) P70 ANI0 Input P70 = Setting not required PM70 = 1 − − − P71 ANI1 Input P71 = Setting not required PM71 = 1 − − − P72 ANI2 Input P72 = Setting not required PM72 = 1 − − − P73 ANI3 Input P73 = Setting not required PM73 = 1 − − − P74 ANI4 Input P74 = Setting not required
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Pin Name Alternate Function Name P93 P94 P95 P96 P97 Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) TECR0 Input P93 = Setting not required PM93 = Setting not required PMC93 = 1 PFCE93 = 0 PFC93 = 0 TIT00 Input P93 = Setting not required PM93 = Setting not required PMC93 = 1 PFCE93 = 0 PFC93 = 1 TOT00 Output P93 = Setting not required PM93 = Setting not required PMC93 =
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Pin Name Alternate Function Name P99 P911 P912 P913 P914 PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits PMn Register PMCn Register PFCEn Register PFCn Register (Registers) I/O P99 = Setting not required PM99 = Setting not required PMC99 = 1 PFCE99 = 0 PFC99 = 0 INTP13 Input P99 = Setting not required PM99 = Setting not required PMC99 = 1 PFCE99 = 0 PFC99 = 1 A9 Output P99 = Setting not required PM99 = Setting not required PMC99 = 1 PFCE99 = 1 PFC99 = 0 SIF3
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Pin Name Alternate Function Name I/O PCM0 WAITNote Input PCM1 CLKOUT Output Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) PCM0 = Setting not required PMCM0 = Setting not required PMCCM0 = 1 − − PCM1 = Setting not required PMCM1 = Setting not required PMCCM1 = 1 − − HLDAK Output PCM2 = Setting not required PMCM2 = Setting not required PMCCM2 = 1 − − PCM3 HLDRQNote Inpu
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Pin Name Alternate Function Name I/O Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) AD5 I/O PDL5 = Setting not required PMDL5 = Setting not required PMCDL5 = 1 − − FLMD1Note Input PDL5 = Setting not required PMDL5 = Setting not required PMCDL5 = Setting not required − − PDL6 AD6 I/O PDL6 = Setting not required PMDL6 = Setting not required PMCDL6 = 1 − − PDL7 AD7 I
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V850ES/JG3-H, V850ES/JH3-H 4.5 4.5.1 CHAPTER 4 PORT FUNCTIONS Cautions Cautions on setting port pins (1) In the V850ES/JG3-H and V850ES/JH3-H, the general-purpose port functions share pins with several peripheral function I/O pins. Switch between the general-purpose port (port mode) and the peripheral function I/O pin (alternate-function mode) by setting the PMCn register. Note the following cautions with regards to this register setting sequence.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS The setting procedure that may cause malfunction on switching from the P41 pin to the SCL01 pin is shown below.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS Figure 4-4.
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V850ES/JG3-H, V850ES/JH3-H 4.5.2 CHAPTER 4 PORT FUNCTIONS Cautions on bit manipulation instruction for port n register (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the value of the output latch of an input port that is not subject to manipulation may be written in addition to the targeted bit. Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode.
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V850ES/JG3-H, V850ES/JH3-H 4.5.3 CHAPTER 4 PORT FUNCTIONS Cautions on on-chip debug pins (V850ES/JG3-H only) The DRST, DCK, DMS, DDI, and DDO pins are on-chip debug pins. After reset by the RESET pin, the P56/INTP05/DRST pin is initialized to function as an on-chip debug pin (DRST). If a high level is input to the DRST pin at this time, the on-chip debug mode is set, and the DCK, DMS, DDI, and DDO pins can be used. The following action must be taken if on-chip debugging is not used.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 5 BUS CONTROL FUNCTION CHAPTER 5 BUS CONTROL FUNCTION The V850ES/JG3-H and V850ES/JH3-H are provided with an external bus interface function by which external memories such as ROM and RAM, and I/O can be connected. 5.1 Features Output is selectable from multiplexed bus output with a minimum of 3 bus cycles and separate bus output (V850ES/JH3-H only; the V850ES/JG3-H only supports the multiplexed bus.
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V850ES/JG3-H, V850ES/JH3-H 5.2 CHAPTER 5 BUS CONTROL FUNCTION Bus Control Pins The pins used to connect an external device are listed in the table below. Table 5-1.
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V850ES/JG3-H, V850ES/JH3-H 5.2.1 CHAPTER 5 BUS CONTROL FUNCTION Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed When the internal ROM, internal RAM, or on-chip peripheral I/O are accessed, the status of each pin is as follows. Table 5-4.
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V850ES/JG3-H, V850ES/JH3-H 5.3 CHAPTER 5 BUS CONTROL FUNCTION Memory Block Function The 16 MB external memory space is divided into memory blocks of 2 MB, 4 MB, and 8 MB from the lowest of the memory space. The programmable wait function and bus cycle operation mode for each of these blocks can be independently controlled in one-block units. Figure 5-1.
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V850ES/JG3-H, V850ES/JH3-H 5.4 5.4.1 CHAPTER 5 BUS CONTROL FUNCTION Bus Access Number of clocks for access The following table shows the number of basic clocks required for accessing each resource. Area (Bus Width) Internal ROM (32 Bits) Internal RAM (32 Bits) Bus Cycle Type External Memory (16 Bits) Multiplexed Instruction fetch (normal access) 1 Instruction fetch (branch) 3 Operand data access 5 Note 2 3+n Note 1 3+n 1 2 Note 1 Separate 1 3+n Notes 1. V850ES/JH3-H only 2.
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V850ES/JG3-H, V850ES/JH3-H 5.4.3 CHAPTER 5 BUS CONTROL FUNCTION Access by bus size The V850ES/JG3-H and V850ES/JH3-H access the on-chip peripheral I/O and external memory in 8-bit, 16-bit, or 32bit units. The bus size is as follows. • The bus size of the on-chip peripheral I/O is fixed to 16 bits. • The bus size of the external memory is selectable from 8 bits or 16 bits (by using the BSC register). The operation when each of the above is accessed is described below.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 5 BUS CONTROL FUNCTION (2) Byte access (8 bits) (a) 16-bit data bus width <1> Access to even address (2n) <2> Access to odd address (2n + 1) Address Address 15 15 7 8 7 7 8 7 0 0 0 0 2n + 1 2n Byte data External data bus Byte data External data bus (b) 8-bit data bus width <1> Access to even address (2n) <2> Access to odd address (2n + 1) Address Address 7 7 0 0 7 7 0 0 2n + 1 2n Byte data External data bus R01UH0042EJ0500 Rev.5.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 5 BUS CONTROL FUNCTION (3) Halfword access (16 bits) (a) 16-bit data bus width <1> Access to even address (2n) <2> Access to odd address (2n + 1) First access Address 15 15 Address 2n + 1 8 7 8 7 15 15 8 7 8 7 Address 15 15 8 7 8 7 2n + 1 2n 0 Second access 2n + 2 2n 0 0 Halfword data External data bus 0 Halfword data 0 External data bus 0 Halfword data External data bus (b) 8-bit data bus width <1> Access to even address (2n) First access
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 5 BUS CONTROL FUNCTION (4) Word access (32 bits) (a) 16-bit data bus width (1/2) <1> Access to address (4n) First access Second access 31 31 24 23 24 23 Address 16 15 15 8 7 8 7 0 0 Address 16 15 15 8 7 8 7 0 0 4n + 1 4n + 3 4n Word data External data bus 4n + 2 Word data External data bus <2> Access to address (4n + 1) First access Second access Third access 31 31 31 24 23 24 23 24 23 Address 16 15 15 8 7 0 Address 16 15 15 8 7
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 5 BUS CONTROL FUNCTION (a) 16-bit data bus width (2/2) <3> Access to address (4n + 2) First access Second access 31 31 24 23 24 23 Address 16 15 15 8 7 8 7 Address 16 15 15 8 7 8 7 4n + 3 4n + 5 4n + 2 0 0 4n + 4 0 Word data External data bus 0 Word data External data bus <4> Access to address (4n + 3) First access Second access Third access 31 31 31 24 23 24 23 24 23 Address 16 15 15 8 7 0 Address 16 15 15 8 7 8 7 8 7 0 0 0
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 5 BUS CONTROL FUNCTION (b) 8-bit data bus width (1/2) <1> Access to address (4n) First access Second access Third access Fourth access 31 31 31 31 24 23 24 23 24 23 24 23 16 15 16 15 16 15 16 15 Address 8 7 7 0 0 Address 8 7 7 0 0 4n Word data External data bus Address 8 7 7 0 0 4n + 1 Word data External data bus Address 8 7 7 0 0 4n + 2 Word data External data bus 4n + 3 Word data External data bus <2> Access to address (4n + 1)
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 5 BUS CONTROL FUNCTION (b) 8-bit data bus width (2/2) <3> Access to address (4n + 2) First access Second access Third access Fourth access 31 31 31 31 24 23 24 23 24 23 24 23 16 15 16 15 16 15 16 15 8 7 Address 7 4n + 2 0 0 Word data External data bus Address 8 7 7 4n + 3 0 0 Word data External data bus 8 7 Address 7 4n + 4 0 0 Word data External data bus 8 7 Address 7 4n + 5 0 0 Word data External data bus <4> Access to address (4n + 3) Fir
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V850ES/JG3-H, V850ES/JH3-H 5.5 5.5.1 CHAPTER 5 BUS CONTROL FUNCTION Wait Function Programmable wait function (1) Data wait control register 0 (DWC0) To realize interfacing with a low-speed memory or I/O, up to seven data wait states can be inserted in the bus cycle that is executed for each CS space. The number of wait states can be programmed by using the DWC0 register. Immediately after system reset, 7 data wait states are inserted for all the blocks.
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V850ES/JG3-H, V850ES/JH3-H 5.5.2 CHAPTER 5 BUS CONTROL FUNCTION External wait function To synchronize an extremely slow external memory, I/O, or asynchronous system, any number of wait states can be inserted in the bus cycle by using the external wait pin (WAIT). When the P60Note 1 or PCM0Note 2 pin is set to its alternate function, the external wait function is enabled.
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V850ES/JG3-H, V850ES/JH3-H 5.5.3 CHAPTER 5 BUS CONTROL FUNCTION Relationship between programmable wait and external wait Wait cycles are inserted as the result of an OR operation between the wait cycles specified by the set value of the programmable wait and the wait cycles controlled by the WAIT pin. Programmable wait Wait control Wait via WAIT pin For example, if the timing of the programmable wait and the WAIT pin signal is as illustrated below, three wait states will be inserted in the bus cycle.
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V850ES/JG3-H, V850ES/JH3-H 5.5.4 CHAPTER 5 BUS CONTROL FUNCTION Programmable address wait function Address-setup or address-hold waits to be inserted in each bus cycle can be set by using the AWC register. Address wait insertion is set for each chip select area (CS0, CS2, CS3). If an address setup wait is inserted, it seems that the high-clock period of the T1 state is extended by 1 clock. If an address-hold wait is inserted, it seems that the low-clock period of the T1 state is extended by 1 clock.
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V850ES/JG3-H, V850ES/JH3-H 5.6 CHAPTER 5 BUS CONTROL FUNCTION Idle State Insertion Function To facilitate interfacing with low-speed memories, one idle state (TI) can be inserted after the T3 state in the bus cycle that is executed for each space selected by the chip select. By inserting an idle state, the data output float delay time of the memory can be secured during read access (an idle state cannot be inserted during write access).
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V850ES/JG3-H, V850ES/JH3-H 5.7 5.7.1 CHAPTER 5 BUS CONTROL FUNCTION Bus Hold Function (V850ES/JH3-H only) Functional outline The HLDRQ and HLDAK functions are valid if the PCM2 and PCM3 pins are set to their alternate function. When the HLDRQ pin is asserted (low level), indicating that another bus master has requested bus mastership, the external address/data bus goes into a high-impedance state and is released (bus hold status).
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V850ES/JG3-H, V850ES/JH3-H 5.7.2 CHAPTER 5 BUS CONTROL FUNCTION Bus hold procedure The bus hold status transition procedure is shown below. <1> HLDRQ = 0 acknowledged <2> All bus cycle start requests inhibited Normal status <3> End of current bus cycle <4> Shift to bus idle status <5> HLDAK = 0 Bus hold status <6> HLDRQ = 1 acknowledged <7> HLDAK = 1 <8> Bus cycle start request inhibition released <9> Bus cycle starts Normal status HLDRQ (input) HLDAK (output) <1> <2> <3><4> <5> 5.7.
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V850ES/JG3-H, V850ES/JH3-H 5.8 CHAPTER 5 BUS CONTROL FUNCTION Bus Priority Bus hold, DMA transfer, operand data accesses, instruction fetch (branch), and instruction fetch (successive) are executed in the external bus cycle. Bus hold has the highest priority, followed by DMA transfer, operand data access, instruction fetch (branch), and instruction fetch (successive). An instruction fetch may be inserted between the read access and write access in a read-modify-write access.
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V850ES/JG3-H, V850ES/JH3-H 5.9 CHAPTER 5 BUS CONTROL FUNCTION Bus Timing Figure 5-4. Multiplexed/Separate Bus Read Timing (Bus Size: 16 Bits, 16-Bit Access) T1 T2 T3 T1 T2 TW TW T3 TI T1 CLKOUT A23 to A0Note 1 A1 A2 A3 D2 A3 ASTB CS3, CS2, CS0Note 2 WAIT AD15 to AD0 A1 A2 D1 RD Programmable External wait wait 8-bit Access Idle state Odd Address Even Address AD15 to AD8 Active Hi-Z AD7 to AD0 Hi-Z Active Notes 1. V850ES/JH3-H only 2.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 5 BUS CONTROL FUNCTION Figure 5-6. Multiplexed/Separate Bus Write Timing (Bus Size: 16 Bits, 16-Bit Access) T1 T2 T3 T1 T2 TW TW T3 T1 CLKOUT A23 to A0Note 1 A1 A2 A3 D2 A3 ASTB CS3, CS2, CS0Note 2 WAIT A1 AD15 to AD0 WR1, WR0 11 D1 A2 11 00 8-bit Access 11 Programmable External wait wait Odd Address Even Address AD15 to AD8 Active Hi-Z AD7 to AD0 Undefined Active WR1, WR0 01 10 11 00 Notes 1. V850ES/JH3-H only 2.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 5 BUS CONTROL FUNCTION Figure 5-8. Multiplexed/Separate Bus Hold Timing (Bus Size: 16 Bits, 16-Bit Access) (V850ES/JH3-H only) T1 T2 T3 TINote 1 TH TH TH TH TINote 1 T1 T2 T3 CLKOUT HLDRQ HLDAK A23 to A0 A1 AD15 to AD0 A1 Undefined Undefined D1 Undefined Undefined 1111 1111 A2 A2 D2 ASTB RD CS3, CS2, CS0Note 2 Notes 1. This idle state (TI) does not depend on the BCC register settings. 2. Only the CS space subject to access is active. Remarks 1.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 6 CLOCK GENERATION FUNCTION CHAPTER 6 CLOCK GENERATION FUNCTION 6.1 Overview The following clock generation functions are available. Main clock oscillator • In clock-through mode fX = 3.0 to 6.0 MHz (fXX = 3.0 to 6.0 MHz) • In PLL mode fX = 3.0 to 6.0 MHz (×8: fXX = 24 to 48 MHz) Subclock oscillator • fXT = 32.768 kHz Multiply (×8) function by PLL (Phase Locked Loop) • Clock-through mode/PLL mode selectable Internal oscillator • fR = 220 kHz (TYP.
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V850ES/JG3-H, V850ES/JH3-H 6.2 CHAPTER 6 CLOCK GENERATION FUNCTION Configuration Figure 6-1.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 6 CLOCK GENERATION FUNCTION (1) Main clock oscillator The main clock oscillator oscillates the following frequencies (fX). • In clock-through mode fX = 3.0 to 6.0 MHz • In PLL mode fX = 3.0 to 6.0 MHz (×8) (2) Subclock oscillator The sub-resonator oscillates a frequency of 32.768 kHz (fXT). (3) Main clock oscillator stop control This circuit generates a control signal that stops oscillation of the main clock oscillator.
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V850ES/JG3-H, V850ES/JH3-H 6.3 CHAPTER 6 CLOCK GENERATION FUNCTION Registers (1) Processor clock control register (PCC) The PCC register is a special register. Data can be written to this register only in combination of specific sequences (see 3.4.8 Special registers). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 03H. R01UH0042EJ0500 Rev.5.
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V850ES/JG3-H, V850ES/JH3-H After reset: 03H CHAPTER 6 CLOCK GENERATION FUNCTION R/W Address: FFFFF828H < > < > PCC FRC MCK MFRC FRC Note CLS < > CK3 CK2 CK1 CK0 Use of subclock on-chip feedback resistor 0 Used 1 Not used MCK Main clock oscillator control 0 Oscillation enabled 1 Oscillation stopped • Even if the MCK bit is set (1) while the system is operating with the main clock as the CPU clock, the operation of the main clock does not stop.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 6 CLOCK GENERATION FUNCTION (a) Example of setting main clock operation → subclock operation <1> CK3 bit ← 1: Use of a bit manipulation instruction is recommended. Do not change the CK2 to CK0 bits. <2> Subclock operation: Read the CLS bit to check if subclock operation has started. It takes the following time after the CK3 bit is set until subclock operation is started. Max.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 6 CLOCK GENERATION FUNCTION (b) Example of setting subclock operation → main clock operation <1> MCK bit ← 0: Main clock starts oscillating <2> Insert waits by the program and wait until the oscillation stabilization time of the main clock elapses. <3> CK3 bit ← 0: Use of a bit manipulation instruction is recommended. Do not change the CK2 to CK0 bits.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 6 CLOCK GENERATION FUNCTION (2) Internal oscillation mode register (RCM) The RCM register is an 8-bit register that sets the operation mode of the internal oscillator. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W Address: FFFFF80CH < > RCM 0 0 0 RSTOP 0 0 0 0 RSTOP Oscillation/stop of internal oscillator 0 Internal oscillator oscillation 1 Internal oscillator stopped Cautions 1.
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V850ES/JG3-H, V850ES/JH3-H 6.4 6.4.1 CHAPTER 6 CLOCK GENERATION FUNCTION Operation Operation of each clock The following table shows the operation status of each clock. Table 6-1.
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V850ES/JG3-H, V850ES/JH3-H 6.5 6.5.1 CHAPTER 6 CLOCK GENERATION FUNCTION PLL Function Overview In the V850ES/JG3-H and V850ES/JH3-H, an operating clock that is 8 times higher than the oscillation frequency output by the PLL function or the clock-through mode can be selected as the operating clock of the CPU and on-chip peripheral functions. When PLL function is used (×8): Input clock = 3.0 to 6.0 MHz (output: 24 to 48 MHz) Clock-through mode: 6.5.2 Input clock = 3.0 to 6.0 MHz (output: 3.0 to 6.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 6 CLOCK GENERATION FUNCTION (2) Clock control register (CKC) The CKC register is a special register. Data can be written to this register only in a combination of specific sequence (see 3.4.8 Special registers). The CKC register controls the internal system clock in the PLL mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 0AH. After reset: 0AH CKC 0 R/W 0 CKDIV0 Caution 1.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 6 CLOCK GENERATION FUNCTION (3) Lock register (LOCKR) Phase lock occurs at a given frequency following power application or immediately after the STOP mode is released, and the time required for stabilization is the lockup time (frequency stabilization time). This state until stabilization is called the lockup status, and the stabilized state is called the locked status. The LOCKR register includes a LOCK bit that reflects the PLL frequency stabilization status.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 6 CLOCK GENERATION FUNCTION (4) PLL lockup time specification register (PLLS) The PLLS register is an 8-bit register used to select the PLL lockup time when the PLLCTL.PLLON bit is changed from 0 to 1. This register can be read or written in 8-bit units. Reset sets this register to 03H.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Timer AA (TAA) is 16-bit timer/event counter. The V850ES/JG3-H and V850ES/JH3-H have TAA0 to TAA5. 7.1 Overview An overview of TAAn is shown below.
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V850ES/JG3-H, V850ES/JH3-H 7.3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Configuration TAAn includes the following hardware. Table 7-1.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (1) 16-bit counter This 16-bit counter can count internal clocks or external events. The count value of this counter can be read by using the TAAnCNT register. When the TAAnCTL0.TAAnCE bit = 0, the value of the 16-bit counter is FFFFH. If the TAAnCNT register is read at this time, 0000H is read. Reset sets the TAAnCE bit to 0. Therefore, the 16-bit counter is set to FFFFH.
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V850ES/JG3-H, V850ES/JH3-H 7.3.1 CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Pin configuration The timer inputs and outputs that configure TAAn are shared with the following ports. The port functions must be set when using each pin (see Table 4-20 When Using Port Pins as Alternate-Function Pins).
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V850ES/JG3-H, V850ES/JH3-H 7.4 CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Registers The registers that control TAAn are as follows.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (1) TAAn control register 0 (TAAnCTL0) The TAAnCTL0 register is an 8-bit register that controls the operation of TAAn. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. The same value can always be written to the TAAnCTL0 register by software.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (2) TAAn control register 1 (TAAnCTL1) The TAAnCTL1 register is an 8-bit register that controls the operation of TAAn. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (2/2) TAAmEEE Count clock selection 0 Disables operation with external event count input. (Performs counting with the count clock selected by the TAAmCTL0.TAAmCK0 to TAAmCK2 bits.) 1 Enables operation with external event count input. (Performs counting at every valid edge of the external event count input signal.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (3) TAAn I/O control register 0 (TAAnIOC0) The TAAnIOC0 register is an 8-bit register that controls the timer output (TOAAn0, TOAAn1 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (4) TAAn I/O control register 1 (TAAnIOC1) The TAAnIOC1 register is an 8-bit register that controls the valid edge of the capture trigger input signals (TIAAn0, TIAAn1 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (5) TAAn I/O control register 2 (TAAnIOC2) The TAAnIOC2 register is an 8-bit register that controls the valid edge of the external event count input signal (TIAAn0 pin) and external trigger input signal (TIAAn0 pin). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W Address: TAA0IOC2 FFFFF634H, TAA1IOC2 FFFFF644H, TAA2IOC2 FFFFF654H, TAA3IOC2 FFFFF664H.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (6) TAAn I/O control register 4 (TAAnIOC4) The TAAnIOC4 register is an 8-bit register that controls the timer output. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. This register is not reset by stopping the timer operation (TAAnCTL0.TAAnCE = 0). Cautions 1. Accessing the TAAnIOC4 register is prohibited in the following statuses. For details, see 3.4.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (7) TAAn option register 0 (TAAnOPT0) The TAAnOPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (8) TAAn option register 1 (TAAnOPT1) The TAAnOPT1 register is an 8-bit register that controls the 32-bit capture function realized by a cascade connection. Rewriting this register is prohibited while the timer is operating (TAAnCTL0.TAAnCE = 1). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (9) TAAn capture/compare register 0 (TAAnCCR0) The TAAnCCR0 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TAAnOPT0.TAAnCCS0 bit. In the pulse width measurement mode, the TAAnCCR0 register can be used only as a capture register.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (a) Function as compare register The TAAnCCR0 register can be rewritten even when the TAAnCTL0.TAAnCE bit = 1. The set value of the TAAnCCR0 register is transferred to the CCR0 buffer register. When the value of the 16bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTAAnCC0) is generated. If TOAAn0 pin output is enabled at this time, the output of the TOAAn0 pin is inverted.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (10) TAAn capture/compare register 1 (TAAnCCR1) The TAAnCCR1 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TAAnOPT0.TAAnCCS1 bit. In the pulse width measurement mode, the TAAnCCR1 register can be used only as a capture register.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (a) Function as compare register The TAAnCCR1 register can be rewritten even when the TAAnCTL0.TAAnCE bit = 1. The set value of the TAAnCCR1 register is transferred to the CCR1 buffer register. When the value of the 16bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTAAnCC1) is generated. If TOAAn1 pin output is enabled at this time, the output of the TOAAn1 pin is inverted.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (11) TAAn counter read buffer register (TAAnCNT) The TAAnCNT register is a read buffer register that can read the count value of the 16-bit counter. If this register is read when the TAAnCTL0.TAAnCE bit = 1, the count value of the 16-bit timer can be read. This register is read-only, in 16-bit units. The value of the TAAnCNT register is cleared to 0000H when the TAAnCE bit = 0.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (12) Noise elimination control register (TANFC) Digital noise elimination can be selected for the TIAAn0 and TIAAn1 pins. The noise elimination setting is selected using the TANFC register. When digital noise elimination is selected, the sampling clock for digital sampling can be selected from among fXX and fXX/4. Sampling is performed 3 times. This register can be read or written in 8-bit units. Reset sets this register to 00H.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) A timing example of noise elimination performed by the timer AA input pin digital filter is shown Figure 7-2. Figure 7-2.
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V850ES/JG3-H, V850ES/JH3-H 7.5 CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Operation TAAn can perform the following operations. Operation Interval timer mode External event count mode Note 1 External trigger pulse output mode One-shot pulse output mode Note 2 Note 2 PWM output mode Free-running timer mode Pulse width measurement mode Note 2 TAAnCTL1.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (1) Anytime write and batch write With TAAn, the TAAnCCR0 and TAAnCCR1 registers can be rewritten during timer operation (TAAnCTL0.TAAnCE bit = 1), but the write method (anytime write, batch write) of the CCR0 and CCR1 buffer registers differs depending on the mode. (a) Anytime write In this mode, data is transferred at any time from the TAAnCCR0 and TAAnCCR1 registers to the CCR0 and CCR1 buffer registers during timer operation.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 7-4. Example of Anytime Write Timing (Interval Timer Mode of TAA0) TAA0CE bit = 1 D01 FFFFH D01 D02 16-bit counter D11 D11 D12 D12 0000H D01 TAA0CCR0 register CCR0 buffer register 0000H D01 D11 TAA0CCR1 register CCR1 buffer register D02 0000H D02 D12 D11 D12 INTTAA0C0 signal INTTAA0CC1 signal Remark D01, D02: Set values of TAA0CCR0 register D11, D12: Set values of TAA0CCR1 register R01UH0042EJ0500 Rev.5.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (b) Batch write In this mode, data is transferred all at once from the TAAnCCR0 and TAAnCCR1 registers to the CCR0 and CCR1 buffer registers during timer operation. This data is transferred upon a match between the value of the CCR0 buffer register and the value of the 16-bit counter. Transfer is enabled by writing to the TAAnCCR1 register.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 7-5.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 7-6.
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V850ES/JG3-H, V850ES/JH3-H 7.5.1 CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Interval timer mode (TAAmMD2 to TAAmMD0 bits = 000) In the interval timer mode, an interrupt request signal (INTTAAnCC0) is generated at any interval if the TAAnCTL0.TAAnCE bit is set to 1. A square wave whose half cycle is equal to the interval can be output from the TOAAn0 pin. Usually, the TAAnCCR1 register is not used in the interval timer mode. Figure 7-7.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) When the TAAnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts counting. At this time, the output of the TOAAn0 pin is inverted. Additionally, the set value of the TAAnCCR0 register is transferred to the CCR0 buffer register.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 7-9.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (1) Interval timer mode operation flow Figure 7-10.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (2) Interval timer mode operation timing (a) Operation if TAAnCCR0 register is set to 0000H If the TAAnCCR0 register is set to 0000H, the INTTAAnCC0 signal is generated at each count clock subsequent to the first count clock, and the output of the TOAAm0 pin is inverted. The value of the 16-bit counter is always 0000H.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (b) Operation if TAAnCCR0 register is set to FFFFH If the TAAnCCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH. The counter is cleared to 0000H in synchronization with the next count-up timing. The INTTAAnCC0 signal is generated and the output of the TOAAm0 pin is inverted. At this time, an overflow interrupt request signal (INTTAAnOV) is not generated, nor is the overflow flag (TAAmOPT0.TAAmOVF bit) set to 1.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (c) Notes on rewriting TAAnCCR0 register To change the value of the TAAnCCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TAAnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (d) Operation of TAAnCCR1 register Figure 7-11. Configuration of TAAnCCR1 Register TAAnCCR1 register CCR1 buffer register Output controller Match signal TOAAn1 pin INTTAAnCC1 signal Clear Count clock selection 16-bit counter Match signal TAAnCE bit Output controller TOAAn0 pin INTTAAnCC0 signal CCR0 buffer register TAAnCCR0 register Remark n = 0 to 3, 5 R01UH0042EJ0500 Rev.5.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) If the set value of the TAAnCCR1 register is less than the set value of the TAAnCCR0 register, the INTTAAnCC1 signal is generated once per cycle. At the same time, the output of the TOAAn1 pin is inverted. The TOAAn1 pin outputs a square wave with the same cycle as that output by the TOAAn0 pin. Figure 7-12.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) If the set value of the TAAnCCR1 register is greater than the set value of the TAAnCCR0 register, the count value of the 16-bit counter does not match the value of the TAAnCCR1 register. Consequently, the INTTAAnCC1 signal is not generated, nor is the output of the TOAAn1 pin changed. Figure 7-13.
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V850ES/JG3-H, V850ES/JH3-H 7.5.2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) External event count mode (TAAnMD2 to TAAnMD0 bits = 001) In the external event count mode, the valid edge of the external event count input is counted when the TAAnCTL0.TAAnCE bit is set to 1, and an interrupt request signal (INTTAAnCC0) is generated each time the specified number of edges have been counted. The TOAAn0 pin cannot be used. Usually, the TAAnCCR1 register is not used in the external event count mode.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) When the TAAnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts each time the valid edge of external event count input is detected. Additionally, the set value of the TAAnCCR0 register is transferred to the CCR0 buffer register.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 7-16. Register Setting for Operation in External Event Count Mode (2/2) (e) TAAn counter read buffer register (TAAnCNT) The count value of the 16-bit counter can be read by reading the TAAnCNT register.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (1) External event count mode operation flow Figure 7-17.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (2) Operation timing in external event count mode Cautions 1. In the external event count mode, do not set the TAAnCCR0 register to 0000H. 2. In the external event count mode, use of the timer output is disabled. If performing timer output using external event count input, set the interval timer mode, and select the operation of the count clock to be enabled by the external event count input (TAAnCTL1.TAAnMD2 to TAAnCTL1.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (b) Notes on rewriting the TAAnCCR0 register To change the value of the TAAnCCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TAAnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (c) Operation of TAAnCCR1 register Figure 7-18.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) If the set value of the TAAnCCR1 register is greater than the set value of the TAAnCCR0 register, the INTTAAnCC1 signal is not generated because the count value of the 16-bit counter and the value of the TAAnCCR1 register do not match. Figure 7-20.
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V850ES/JG3-H, V850ES/JH3-H 7.5.3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) External trigger pulse output mode (TAAnMD2 to TAAnMD0 bits = 010) In the external trigger pulse output mode, 16-bit timer/event counter AA waits for a trigger when the TAAnCTL0.TAAnCE bit is set to 1. When the valid edge of an external trigger input signal is detected, 16-bit timer/event counter AA starts counting, and outputs a PWM waveform from the TOAAn1 pin.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 7-22.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 7-23.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 7-23. Setting of Registers in External Trigger Pulse Output Mode (2/2) (d) TAAn I/O control register 2 (TAAnIOC2) TAAnEES1 TAAnEES0 TAAnETS1 TAAnETS0 TAAnIOC2 0 0 0 0 0 0 0/1 0/1 Select valid edge of external trigger input (e) TAAn counter read buffer register (TAAnCNT) The value of the 16-bit counter can be read by reading the TAAnCNT register.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (1) Operation flow in external trigger pulse output mode Figure 7-24.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 7-24.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (2) External trigger pulse output mode operation timing (a) Note on changing pulse width during operation To change the PWM waveform while the counter is operating, write the TAAnCCR1 register last. Rewrite the TAAnCCRm register after writing the TAAnCCR1 register after the INTTAAnCC0 signal is detected.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) In order to transfer data from the TAAnCCRm register to the CCRm buffer register, the TAAnCCR1 register must be written. To change both the cycle and active level width of the PWM waveform at this time, first set the cycle to the TAAnCCR0 register and then set the active level width to the TAAnCCR1 register.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TAAnCCR1 register to 0000H. If the set value of the TAAnCCR0 register is FFFFH, the INTTAAnCC1 signal is generated periodically.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (c) Conflict between trigger detection and match with TAAnCCR1 register If the trigger is detected immediately after the INTTAAnCC1 signal is generated, the 16-bit counter is cleared to 0000H at the same time, the output signal of the TOAAn1 pin is asserted, and the counter continues counting. Consequently, the inactive period of the PWM waveform is shortened.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (d) Conflict between trigger detection and match with TAAnCCR0 register If the trigger is detected immediately after the INTTAAnCC0 signal is generated, the 16-bit counter is cleared to 0000H again and continues counting up. Therefore, the active period of the TOAAn1 pin is extended by the time from generation of the INTTAAnCC0 signal to trigger detection.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (e) Generation timing of compare match interrupt request signal (INTTAAnCC1) The timing of generation of the INTTAAnCC1 signal in the external trigger pulse output mode differs from the timing of other INTTAAnCC1 signals; the INTTAAnCC1 signal in the external trigger pulse output mode is generated when the count value of the 16-bit counter matches the value of the TAAnCCR1 register.
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V850ES/JG3-H, V850ES/JH3-H 7.5.4 CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) One-shot pulse output mode (TAAnMD2 to TAAnMD0 bits = 011) In the one-shot pulse output mode, 16-bit timer/event counter AA waits for a trigger when the TAAnCTL0.TAAnCE bit is set to 1. When the valid edge of an external trigger input is detected, 16-bit timer/event counter AA starts counting, and outputs a one-shot pulse from the TOAAn1 pin.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 7-26.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 7-27.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 7-27. Register Setting for Operation in One-Shot Pulse Output Mode (2/2) (d) TAAn I/O control register 2 (TAAnIOC2) TAAnEES1 TAAnEES0 TAAnETS1 TAAnETS0 TAAnIOC2 0 0 0 0 0 0 0/1 0/1 Select valid edge of external trigger input (e) TAAn counter read buffer register (TAAnCNT) The value of the 16-bit counter can be read by reading the TAAnCNT register.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (1) Operation flow in one-shot pulse output mode Figure 7-28.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (2) Operation timing in one-shot pulse output mode (a) Note on rewriting TAAnCCRm register To change the set value of the TAAnCCRm register to a smaller value, stop counting once, and then change the set value. If the value of the TAAnCCRm register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (b) Generation timing of compare match interrupt request signal (INTTAAnCC1) The generation timing of the INTTAAnCC1 signal in the one-shot pulse output mode is different from other INTTAAnCC1 signals; the INTTAAnCC1 signal in the one-shot pulse output mode is generated when the count value of the 16-bit counter matches the value of the TAAnCCR1 register.
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V850ES/JG3-H, V850ES/JH3-H 7.5.5 CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) PWM output mode (TAAnMD2 to TAAnMD0 bits = 100) In the PWM output mode, a PWM waveform is output from the TOAAn1 pin when the TAAnCTL0.TAAnCE bit is set to 1. In addition, a pulse with one cycle of the PWM waveform as half its cycle is output from the TOAAn0 pin. Figure 7-29.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 7-30.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 7-31.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 7-31. Setting of Registers in PWM Output Mode (2/2) (d) TAAn I/O control register 2 (TAAnIOC2) TAAnEES1 TAAnEES0 TAAnETS1 TAAnETS0 TAAnIOC2 0 0 0 0 0/1 0/1 0 0 Select valid edge of external event count input. (e) TAAn counter read buffer register (TAAnCNT) The value of the 16-bit counter can be read by reading the TAAnCNT register.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (1) Operation flow in PWM output mode Figure 7-32.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 7-32.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (2) PWM output mode operation timing (a) Changing pulse width during operation To change the PWM waveform while the counter is operating, write the TAAnCCR1 register last. Rewrite the TAAnCCRm register after writing the TAAnCCR1 register after the INTTAAnCC1 signal is detected.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TAAnCCR1 register to 0000H. If the set value of the TAAnCCR0 register is FFFFH, the INTTAAnCC1 signal is generated periodically.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (c) Generation timing of compare match interrupt request signal (INTTAAnCC1) The timing of generation of the INTTAAnCC1 signal in the PWM output mode differs from the timing of other INTTAAnCC1 signals; the INTTAAnCC1 signal in the PWM output mode is generated when the count value of the 16-bit counter matches the value of the TAAnCCR1 register.
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V850ES/JG3-H, V850ES/JH3-H 7.5.6 CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Free-running timer mode (TAAnMD2 to TAAnMD0 bits = 101) In the free-running timer mode, 16-bit timer/event counter AA starts counting when the TAAnCTL0.TAAnCE bit is set to 1. At this time, the TAAnCCRm register can be used as a compare register or a capture register, depending on the setting of the TAAnOPT0.TAAnCCS0 and TAAnOPT0.TAAnCCS1 bits. Figure 7-33.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) When the TAAnCE bit is set to 1, 16-bit timer/event counter AA starts counting, and the output signals of the TOAAn0 and TOAAn1 pins are inverted. When the count value of the 16-bit counter later matches the set value of the TAAnCCRm register, a compare match interrupt request signal (INTTAAnCCm) is generated, and the output signal of the TOAAnm pin is inverted.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) When the TAAnCE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIAAnm pin is detected, the count value of the 16-bit counter is stored in the TAAnCCRm register, and a capture interrupt request signal (INTTAAnCCm) is generated. The 16-bit counter continues counting in synchronization with the count clock.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 7-36. Register Setting in Free-Running Timer Mode (1/2) (a) TAAn control register 0 (TAAnCTL0) TAAnCE TAAnCTL0 0/1 TAAnCKS2 TAAnCKS1 TAAnCKS0 0 0 0 0 0/1 0/1 0/1 Select count clockNote 0: Stops counting 1: Enables counting Note The setting is invalid when the TAAnCTL1.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 7-36.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (1) Operation flow in free-running timer mode (a) When using capture/compare register as compare register Figure 7-37.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 7-37. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2) <1> Count operation start flow START Register initial setting TAAnCTL0 register (TAAnCKS0 to TAAnCKS2 bits), TAAnCTL1 register, TAAnIOC0 register, TAAnIOC2 register, TAAnOPT0 register, TAAnCCR0 register, TAAnCCR1 register TAAnCE bit = 1 Initial setting of these registers is performed before setting the TAAnCE bit to 1.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (b) When using capture/compare register as capture register Figure 7-38.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 7-38. Software Processing Flow in Free-Running Timer Mode (Capture Function) (2/2) <1> Count operation start flow START Register initial setting TAAnCTL0 register (TAAnCKS0 to TAAnCKS2 bits), TAAnCTL1 register, TAAnIOC1 register, TAAnOPT0 register TAAnCE bit = 1 Initial setting of these registers is performed before setting the TAAnCE bit to 1.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (2) Operation timing in free-running timer mode (a) Interval operation with TAAnCCRm register used as compare register When 16-bit timer/event counter AA is used as an interval timer with the TAAnCCRm register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the INTTAAnCCm signal has been detected.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (b) Pulse width measurement with TAAnCCRm used as capture register When pulse width measurement is performed with the TAAnCCRm register used as a capture register, software processing is necessary for reading the capture register each time the INTTAAnCCm signal has been detected and for calculating the interval.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (c) Processing of overflow when two capture registers are used Care must be exercised in processing the overflow flag when two capture registers are used. First, an example of incorrect processing is shown below.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (1/2) Example when two capture registers are used (using overflow interrupt) FFFFH D11 D10 16-bit counter D01 D00 0000H TAAnCE bit INTTAAnOV signal TAAnOVF bit TAAnOVF0 flagNote TIAAn0 pin input D01 D00 TAAnCCR0 register TAAnOVF1 flagNote TIAAn1 pin input D11 D10 TAAnCCR1 register <1> <2> <3> <4> <5> <6> Note The TAAnOVF0 and TAAnOVF1 flags are set on the internal RAM by software.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (2/2) Example when two capture registers are used (without using overflow interrupt) FFFFH D11 D10 16-bit counter D01 D00 0000H TAAnCE bit INTTAAnOV signal TAAnOVF bit TAAnOVF0 flagNote TIAAn0 pin input D01 D00 TAAnCCR0 register TAAnOVF1 flagNote TIAAn1 pin input D11 D10 TAAnCCR1 register <1> <2> <3> <4> <5> <6> Note The TAAnOVF0 and TAAnOVF1 flags are set on the internal RAM by software.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (d) Processing of overflow if capture trigger interval is long If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once from the first capture trigger to the next. First, an example of incorrect processing is shown below.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Example when capture trigger interval is long FFFFH Dm0 16-bit counter Dm1 0000H TAAnCE bit TIAAnm pin input TAAnCCRm register Dm0 Dm1 INTTAAnOV signal TAAnOVF bit Overflow counterNote 0H 1H 2H 0H 1 cycle of 16-bit counter Pulse width <1> <2> <3> <4> Note The overflow counter is set arbitrarily by software on the internal RAM. <1> Read the TAAnCCRm register (setting of the default value of the TIAAnm pin input).
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (e) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TAAnOVF bit to 0 with the CLR instruction and by writing 8-bit data (bit 0 is 0) to the TAAnOPT0 register. To accurately detect an overflow, read the TAAnOVF bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction.
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V850ES/JG3-H, V850ES/JH3-H 7.5.7 CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Pulse width measurement mode (TAAnMD2 to TAAnMD0 bits = 110) In the pulse width measurement mode, 16-bit timer/event counter AA starts counting when the TAAnCTL0.TAAnCE bit is set to 1. Each time the valid edge input to the TIAAnm pin has been detected, the count value of the 16-bit counter is stored in the TAAnCCRm register, and the 16-bit counter is cleared to 0000H.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 7-40. Basic Timing in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TAAnCE bit TIAAnm pin input TAAnCCRm register 0000H D0 D1 D2 D3 INTTAAnCCm signal INTTAAnOV signal TAAnOVF bit Remark Cleared to 0 by CLR instruction n = 0 to 3, 5 m = 0, 1 When the TAAnCE bit is set to 1, the 16-bit counter starts counting.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 7-41.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (1) Operation flow in pulse width measurement mode Figure 7-42.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (2) Operation timing in pulse width measurement mode (a) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TAAnOVF bit to 0 with the CLR instruction and by writing 8-bit data (bit 0 is 0) to the TAAnOPT0 register. To accurately detect an overflow, read the TAAnOVF bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction.
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V850ES/JG3-H, V850ES/JH3-H 7.5.8 CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Timer output operations The following table shows the operations and output levels of the TOAAn0 and TOAAn1 pins. Table 7-5.
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V850ES/JG3-H, V850ES/JH3-H 7.6 CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Timer-Tuned Operation Function Timer AA and timer AB have a timer-tuned operation function. The timer-tuned operation function is used to tune the internal timers of the V850ES/JG3-H and V850ES/JH3-H, so that the number of capture or compare registers of the slave timer (the number of timer outputs and the number of compare match interrupts of the slave timer) can be added to the master timer.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Table 7-8 show the timer modes that can be used in the tuned-operation mode and Table 7-9 shows the differences of the timer output functions between individual operation and tuned operation (√: Settable, ×: Not settable). Table 7-8. Timer Modes Usable in Tuned-Operation Mode Master Timer Slave Timer Free-Running Timer Mode PWM Mode TAA1 TAA0 √ √ TAA3 TAA2 √ √ TAB0 TAA5 √ √ Table 7-9.
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V850ES/JG3-H, V850ES/JH3-H 7.6.1 CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Free-running timer mode (during timer-tuned operation) This section explains the free-running timer mode of the timer-tuned operation. For the combination of timer-tuned operations, see Table 7-7. In this section, an example of timer-tuned operation using TAA1 and TAA0 is shown.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (1) Settings in free-running timer mode (compare function) [Initial settings] Master timer: TAA1CTL0.TAA1CE = 0 (operation disabled) Slave timer: TAA0CTL0.TAA0CE = 0 (operation disabled) [Initial settings of master timer (TAA1)] • TAA1CTL1.TAA1MD2 to TAA1CTL1.TAA1MD0 = 101 (setting of free-running timer mode) • TAA1OPT0.TAA1CCS1 and TAA1OPT0.TAA1CCS0 = 00 (setting of capture/compare select bit to “compare”.) • TAA1CTL1.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 7-44. Example of Timing in Free-Running Mode (Compare Function) FFFFH D01 D01 D00 D00 TAA1 16-bit counter D11 D11 D10 D10 0000H TAA1CE TAA1CCR0 D10 TAA1CCR1 D11 TAA0CCR0 D00 TAA0CCR1 D01 INTTAA1CC0 INTTAA1CC1 INTTAA0CC0 INTTAA0CC1 INTTAA1OV TAA1OVF TAA1OVF write clear (0) TOAA10 TOAA11 TOAA00 TOAA01 INTTAA0OV L TAA0OVF L R01UH0042EJ0500 Rev.5.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (2) Settings in free-running timer mode (capture function) [Initial settings] Master timer: TAA1CTL0.TAA1CE = 0 (operation disabled) Slave timer: TAA0CTL0.TAA0CE = 0 (operation disabled) [Initial settings of master timer (TAA1)] • TAA1CTL1.TAA1MD2 to TAA1CTL1.TAA1MD0 = 101 (setting of free-running timer mode) • TAA1OPT0.TAA1CCS1 and TAA1OPT0.TAA1CCS0 = 11 (setting of capture/compare select bit to “capture”.) • TAA1CTL1.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 7-45. Example of Timing in Free-Running Mode (Capture Function) FFFFH D011 D110 D001 D000 TAA1 16-bit counter D111 D110 D100 D101 0000H TAA1CE TIAA10 TIAA11 TIAA00 TIAA01 TAA1CCR0 TAA1CCR1 0000 0000 TAA0CCR0 D110 0000 TAA0CCR1 D101 D100 0000 D101 D110 D111 D000 D001 D010 D011 INTTAA1CC0 INTTAA1CC1 INTTAA0CC0 INTTAA0CC1 INTTAA1OV TAA1OVF INTTAA0OV L TAA0OVF L R01UH0042EJ0500 Rev.5.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) (3) Settings in free-running timer mode (capture/compare used together) An example of using TAA0 as a capture register and TAA1 as a compare register is shown below. [Initial settings] Master timer: TAA1CTL0.TAA1CE = 0 (operation disabled) Slave timer: TAA0CTL0.TAA0CE = 0 (operation disabled) [Initial settings of master timer (TAA1)] • TAA1CTL1.TAA1MD2 to TAA1CTL1.TAA1MD0 = 101 (setting of free-running timer mode) • TAA1OPT0.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 7-46. Example of Timing in Free-Running Mode (Capture/Compare Used Together) FFFFH D100 D010 D010 TAA1 16-bit counter D000 D000 D111 D110 0000H TAA1CE TIAA10 TIAA11 0000 TAA1CCR0 TAA1CCR1 0000 D000 D111 D110 TAA0CCR0 0000 D000 TAA0CCR1 0000 D010 INTTAA1CC0 INTTAA1CC1 INTTAA0CC0 INTTAA0CC1 INTTAA1OV TAA1OVF TAA1OVF write clear (0) TOAA00 TOAA01 INTTAA0OV L TAA0OVF L R01UH0042EJ0500 Rev.5.
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V850ES/JG3-H, V850ES/JH3-H 7.6.2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) PWM output mode (during timer-tuned operation) This section explains the PWM output mode of timer-tuned operation. For combinations of timer-tuned operations, see Table 7-7. This section presents an example of a timer-tuned operation with TAB0 and TAA5.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) [Batch write] In the PWM output mode, the next batch write is enabled by writing the TAB0CCR1 register of the master timer (TAB0). After all the compare registers that must be rewritten have been rewritten, therefore, the TAB0CCR1 register of the master timer (TAB0) must be written. Batch writing is executed when the value of the timer counter matches the value of the compare register for cycle (TAB0CCR0).
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V850ES/JG3-H, V850ES/JH3-H 7.7 CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Simultaneous-Start Function Timer AA and timer AB have a timer-tuned operation function. By using the simultaneous-start function, a timer operation in which the operation start timing and count up timing of the master timer and slave timer are synchronized can be performed. Only the PWM output mode can be used in the simultaneous-start function.
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V850ES/JG3-H, V850ES/JH3-H 7.7.1 CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) PWM output mode (simultaneous-start operation) In this section, the operation of the simultaneous-start function is shown, where TAA1 is used as the master timer and TAA0 is used as the slave timer. The master timer (TAA1) and slave timer (TAA0) start operating at the same time when the TAA1CTL0.TAA0CE bit of master timer is set to 1. The slave timer operates by the count clock supplied from the master timer (TAA1).
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 7-49.
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V850ES/JG3-H, V850ES/JH3-H 7.8 CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Cascade Connection This section explains an operation of connecting two channels of TAA in cascade to form a 32-bit capture timer. For cascade connection, the free-running timer mode must be set and all the capture/compare registers must be set as capture registers (TAA0CCSn = 1). Combinations of TAA channels that can be connected in cascade are shown in the following table. Table 7-11.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) The operation of each pin and signal when TAA1 and TAA0 are connected in cascade is shown below. Table 7-12. Status in Cascade Connection Name TIAA10 pin input Higher/Lower Lower Function Capture input 0 Operation The value of the lower timer counter is stored in the TAA1CCR0 register and the value of the higher timer counter is stored in the TAA0CCR0 register when the valid edge of this input is detected.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 7-51.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 7-51.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 7-52.
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V850ES/JG3-H, V850ES/JH3-H 7.9 CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Selector Function In the V850ES/JG3-H and V850ES/JH3-H, the alternate-function pins of ports or peripheral I/O (TAA1, TAB0, UARTC0, or UARTC1) signals can be selected as the capture trigger input of TAA1 and TAB0. If the signal input from the UARTCn pin is selected by the selector function when RXDCn is used, baud rate errors of the LIN reception transfer rate of UARTCn can be calculated (n = 0, 1).
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) 7.10 Cautions (1) Capture operation When the capture operation is used and a slow clock is selected as the count clock, FFFFH, not 0000H, may be captured in the TAAnCCR0 and TAAnCCR1 registers if the capture trigger is input immediately after the TAAnCE bit is set to 1.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) Timer AB (TAB) is a 16-bit timer/event counter. The V850ES/JG3-H and V850ES/JH3-H have TAB0 and TAB1. 8.1 Overview An outline of TABn is shown below.
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V850ES/JG3-H, V850ES/JH3-H 8.3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) Configuration TABn includes the following hardware. Table 8-1.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (1) 16-bit counter This 16-bit counter can count internal clocks or external events. The count value of this counter can be read by using the TABnCNT register. When the TABnCTL0.TABnCE bit = 0, the value of the 16-bit counter is FFFFH. If the TABnCNT register is read at this time, 0000H is read. Reset sets the TABnCE bit to 0. Therefore, the 16-bit counter is set to FFFFH.
PAGE 333
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (7) Output controller This circuit controls the output of the TOABn0 to TOABn3 pins. The output controller is controlled by the TABnIOC0 register. (8) Selector This selector selects the count clock for the 16-bit counter. Eight types of internal clocks or an external event can be selected as the count clock. R01UH0042EJ0500 Rev.5.
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V850ES/JG3-H, V850ES/JH3-H 8.4 CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) Registers The registers that control TABn are as follows.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (1) TABn control register 0 (TABnCTL0) The TABnCTL0 register is an 8-bit register that controls the operation of TABn. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. Software can be used to always write the same value to the TABnCTL0 register.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (2) TABn control register 1 (TABnCTL1) The TABnCTL1 register is an 8-bit register that controls the operation of TABn. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
PAGE 337
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (3) TABn I/O control register 0 (TABnIOC0) The TABnIOC0 register is an 8-bit register that controls the timer output (TOABn0 to TOABn3 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (4) TABn I/O control register 1 (TABnIOC1) The TABnIOC1 register is an 8-bit register that controls the valid edge of the capture trigger input signals (TIABn0 to TIABn3 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
PAGE 339
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (5) TABn I/O control register 2 (TABnIOC2) The TABnIOC2 register is an 8-bit register that controls the valid edge of the external event count input signal (TIAB00/EVTAB1 pin) and external trigger input signal (TIAB00/TRGAB1 pin). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
PAGE 340
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (6) TABn I/O control register 4 (TABnIOC4) The TABnIOC4 register is an 8-bit register that controls the timer output. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. This register is not reset by stopping the timer operation (TABnCTL0.TABnCE = 0). Cautions 1. Accessing the TABnIOC4 register is prohibited in the following statuses. For details, see 3.4.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (7) TABn option register 0 (TABnOPT0) The TABnOPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (8) TABn capture/compare register 0 (TABnCCR0) The TABnCCR0 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, according to the setting of the TABnOPT0.TABnCCS0 bit. In the pulse width measurement mode, the TABnCCR0 register can be used only as a capture register.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (a) Function as compare register The TABnCCR0 register can be rewritten even when the TABnCTL0.TABnCE bit = 1. The set value of the TABnCCR0 register is transferred to the CCR0 buffer register. When the value of the 16bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTABnCC0) is generated. If TOABn0 pin output is enabled at this time, the output of the TOABn0 pin is inverted.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (9) TABn capture/compare register 1 (TABnCCR1) The TABnCCR1 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, according to the setting of the TABnOPT0.TABnCCS1 bit. In the pulse width measurement mode, the TABnCCR1 register can be used only as a capture register.
PAGE 345
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (a) Function as compare register The TABnCCR1 register can be rewritten even when the TABnCTL0.TABnCE bit = 1. The set value of the TABnCCR1 register is transferred to the CCR1 buffer register. When the value of the 16bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTABnCC1) is generated. If TOABn1 pin output is enabled at this time, the output of the TOABn1 pin is inverted.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (10) TABn capture/compare register 2 (TABnCCR2) The TABnCCR2 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, according to the setting of the TABnOPT0.TABnCCS2 bit. In the pulse width measurement mode, the TABnCCR2 register can be used only as a capture register.
PAGE 347
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (a) Function as compare register The TABnCCR2 register can be rewritten even when the TABnCTL0.TABnCE bit = 1. The set value of the TABnCCR2 register is transferred to the CCR2 buffer register. When the value of the 16bit counter matches the value of the CCR2 buffer register, a compare match interrupt request signal (INTTABnCC2) is generated. If TOABn2 pin output is enabled at this time, the output of the TOABn2 pin is inverted.
PAGE 348
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (11) TABn capture/compare register 3 (TABnCCR3) The TABnCCR3 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, according to the setting of the TABnOPT0.TABnCCS3 bit. In the pulse width measurement mode, the TABnCCR3 register can be used only as a capture register.
PAGE 349
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (a) Function as compare register The TABnCCR3 register can be rewritten even when the TABnCTL0.TABnCE bit = 1. The set value of the TABnCCR3 register is transferred to the CCR3 buffer register. When the value of the 16bit counter matches the value of the CCR3 buffer register, a compare match interrupt request signal (INTTABnCC3) is generated. If TOABn3 pin output is enabled at this time, the output of the TOABn3 pin is inverted.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (12) TABn counter read buffer register (TABnCNT) The TABnCNT register is a read buffer register that can read the count value of the 16-bit counter. If this register is read when the TABnCTL0.TABnCE bit = 1, the count value of the 16-bit timer can be read. This register is read-only in 16-bit units. The value of the TABnCNT register is cleared to 0000H when the TABnCE bit = 0.
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V850ES/JG3-H, V850ES/JH3-H 8.5 CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) Operation TABn can perform the following operations. Operation Interval timer mode External event count mode Note 1 External trigger pulse output mode One-shot pulse output mode Note 2 Note 2 PWM output mode Free-running timer mode Pulse width measurement mode Note 2 Triangular wave PWM mode TABnCTL1.
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V850ES/JG3-H, V850ES/JH3-H 8.5.1 CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) Interval timer mode (TABnMD2 to TABnMD0 bits = 000) In the interval timer mode, an interrupt request signal (INTTABnCC0) is generated at the specified interval if the TABnCTL0.TABnCE bit is set to 1. A square wave whose half cycle is equal to the interval can be output from the TOABn0 pin. Usually, the TABnCCR1 to TABnCCR3 registers are not used in the interval timer mode. Figure 8-2.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) When the TABnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts counting. At this time, the output of the TOABn0 pin is inverted. Additionally, the set value of the TABnCCR0 register is transferred to the CCR0 buffer register.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 8-4.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (1) Interval timer mode operation flow Figure 8-5.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (2) Interval timer mode operation timing (a) Operation if TABnCCR0 register is set to 0000H If the TABnCCR0 register is set to 0000H, the INTTABnCC0 signal is generated at each count clock subsequent to the first count clock, and the output of the TOABn0 pin is inverted. The value of the 16-bit counter is always 0000H.
PAGE 357
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (c) Notes on rewriting TABnCCR0 register To change the value of the TABnCCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TABnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
PAGE 358
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (d) Operation of TABnCCR1 to TABnCCR3 registers Figure 8-6.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) If the set value of the TABnCCRk register is less than the set value of the TABnCCR0 register, the INTTABnCCk signal is generated once per cycle. At the same time, the output of the TOABnk pin is inverted. The TOABnk pin outputs a square wave with the same cycle as that output by the TOABn0 pin. Remark k = 1 to 3, n = 0, 1 Figure 8-7.
PAGE 360
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) If the set value of the TABnCCRk register is greater than the set value of the TABnCCR0 register, the count value of the 16-bit counter does not match the value of the TABnCCRk register. Consequently, the INTTABnCCk signal is not generated, nor is the output of the TOABnk pin changed. Remark k = 1 to 3, n = 0, 1 Figure 8-8.
PAGE 361
V850ES/JG3-H, V850ES/JH3-H 8.5.2 CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) External event count mode (TABnMD2 to TABnMD0 bits = 001) In the external event count mode, the valid edge of the external event count input is counted when the TABnCTL0.TABnCE bit is set to 1, and an interrupt request signal (INTTABnCC0) is generated each time the specified number of edges have been counted. The TOABn0 pin cannot be used.
PAGE 362
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) When the TABnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts each time the valid edge of the external event count input is detected. Additionally, the set value of the TABnCCR0 register is transferred to the CCR0 buffer register.
PAGE 363
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 8-11. Register Setting for Operation in External Event Count Mode (2/2) (e) TABn counter read buffer register (TABnCNT) The count value of the 16-bit counter can be read by reading the TABnCNT register.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (1) External event count mode operation flow Figure 8-12.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (2) Operation timing in external event count mode Cautions 1. In the external event count mode, do not set the TABnCCR0 register to 0000H. 2. In the external event count mode, use of the timer output is disabled. If performing timer output using external event count input, set the interval timer mode, and select the operation enabled by the external event count input for the count clock (TABnCTL1.TABnMD2 to TABnCTL1.
PAGE 366
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (b) Notes on rewriting the TABnCCR0 register To change the value of the TABnCCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TABnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
PAGE 367
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (c) Operation of TABnCCR1 to TABnCCR3 registers Figure 8-13.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) If the set value of the TABnCCRk register is smaller than the set value of the TABnCCR0 register, the INTTABnCCk signal is generated once per cycle. Remark k = 1 to 3, n = 0, 1 Figure 8-14.
PAGE 369
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) If the set value of the TABnCCRk register is greater than the set value of the TABnCCR0 register, the INTTABnCCk signal is not generated because the count value of the 16-bit counter and the value of the TABnCCRk register do not match. Remark k = 1 to 3, n = 0, 1 Figure 8-15.
PAGE 370
V850ES/JG3-H, V850ES/JH3-H 8.5.3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) External trigger pulse output mode (TABnMD2 to TABnMD0 bits = 010) In the external trigger pulse output mode, TABn waits for a trigger when the TABnCTL0.TABnCE bit is set to 1. When the valid edge of the external trigger input signal is detected, TABn starts counting, and outputs a PWM waveform from the TOABn1 to TOABn3 pins. Pulses can also be output by generating a software trigger instead of using the external trigger.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 8-17.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) TABn waits for a trigger when the TABnCE bit is set to 1. When the trigger is generated, the 16-bit counter is cleared from FFFFH to 0000H, starts counting at the same time, and outputs a PWM waveform from the TOABnk pin. If the trigger is generated again while the counter is operating, the counter is cleared to 0000H and restarted. (The output of the TOABn0 pin is inverted.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 8-18.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 8-18. Setting of Registers in External Trigger Pulse Output Mode (3/3) (d) TABn I/O control register 2 (TABnIOC2) TABnEES1 TABnEES0 TABnETS1 TABnETS0 TABnIOC2 0 0 0 0 0/1 0/1 0/1 0/1 Select valid edge of external trigger input Select valid edge of external event count input (e) TABn counter read buffer register (TABnCNT) The value of the 16-bit counter can be read by reading the TABnCNT register.
PAGE 375
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (1) Operation flow in external trigger pulse output mode Figure 8-19.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 8-19.
PAGE 377
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (2) External trigger pulse output mode operation timing (a) Note on changing pulse width during operation To change the PWM waveform while the counter is operating, write the TABnCCR1 register last. Rewrite the TABnCCRk register after writing the TABnCCR1 register after the INTTABnCC0 signal is detected.
PAGE 378
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) To transfer data from the TABnCCRm register to the CCRm buffer register, the TABnCCR1 register must be written. To change both the cycle and active level width of the PWM waveform at this time, first set the cycle to the TABnCCR0 register, set the active level width to the TABnCCR2 and TABnCCR3 registers, and then set the active level to the TABnCCR1 register.
PAGE 379
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TABnCCRk register to 0000H. If the set value of the TABnCCR0 register is FFFFH, the INTTABnCCk signal is generated periodically.
PAGE 380
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (c) Conflict between trigger detection and match with CCRk buffer register If the trigger is detected immediately after the INTTABnCCk signal is generated, the 16-bit counter is immediately cleared to 0000H, the output signal of the TOABnk pin is asserted, and the counter continues counting. Consequently, the inactive period of the PWM waveform is shortened.
PAGE 381
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (d) Conflict between trigger detection and match with CCR0 buffer register If the trigger is detected immediately after the INTTABnCC0 signal is generated, the 16-bit counter is cleared to 0000H and continues counting up. Therefore, the active period of the TOABnk pin is extended by time from generation of the INTTABnCC0 signal to trigger detection.
PAGE 382
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (e) Generation timing of compare match interrupt request signal (INTTABnCCk) The timing of generation of the INTTABnCCk signal in the external trigger pulse output mode differs from the timing of other INTTABnCCk signals; the INTTABnCCk signal is generated when the count value of the 16-bit counter matches the value of the CCRk buffer register.
PAGE 383
V850ES/JG3-H, V850ES/JH3-H 8.5.4 CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) One-shot pulse output mode (TABnMD2 to TABnMD0 bits = 011) In the one-shot pulse output mode, TABn waits for a trigger when the TABnCTL0.TABnCE bit is set to 1. When the valid edge of the external trigger input is detected, TABn starts counting, and outputs a one-shot pulse from the TOABn1 to TOABn3 pins. Instead of the external trigger, a software trigger can also be generated to output the pulse.
PAGE 384
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 8-21.
PAGE 385
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) When the TABnCE bit is set to 1, TABn waits for a trigger. When the trigger is generated, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a one-shot pulse from the TOABnk pin. After the one-shot pulse is output, the 16-bit counter is set to FFFFH, stops counting, and waits for a trigger. If a trigger is generated again while the one-shot pulse is being output, it is ignored.
PAGE 386
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 8-22.
PAGE 387
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 8-22. Register Setting for Operation in One-Shot Pulse Output Mode (3/3) (f) TABn capture/compare registers 0 to 3 (TABnCCR0 to TABnCCR3) If D0 is set to the TABnCCR0 register and Dk to the TABnCCRk register, the active level width and output delay period of the one-shot pulse are as follows.
PAGE 388
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (1) Operation flow in one-shot pulse output mode Figure 8-23.
PAGE 389
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 8-23.
PAGE 390
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (2) Operation timing in one-shot pulse output mode (a) Notes on rewriting TABnCCRm register To change the set value of the TABnCCRm register to a smaller value, stop counting once, and then change the set value. If the value of the TABnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
PAGE 391
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (b) Generation timing of compare match interrupt request signal (INTTABnCCk) The generation timing of the INTTABnCCk signal in the one-shot pulse output mode is different from other INTTABnCCk signals; the INTTABnCCk signal is generated when the count value of the 16-bit counter matches the value of the TABnCCRk register.
PAGE 392
V850ES/JG3-H, V850ES/JH3-H 8.5.5 CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) PWM output mode (TABnMD2 to TABnMD0 bits = 100) In the PWM output mode, a PWM waveform is output from the TOABn1 to TOABn3 pins when the TABnCTL0.TABnCE bit is set to 1. In addition, a pulse with one cycle of the PWM waveform as half its cycle is output from the TOABn0 pin. Figure 8-24.
PAGE 393
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 8-25.
PAGE 394
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) When the TABnCE bit is set to 1, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a PWM waveform from the TOABnk pin. The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
PAGE 395
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 8-26.
PAGE 396
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 8-26. Register Setting in PWM Output Mode (3/3) (f) TABn capture/compare registers 0 to 3 (TABnCCR0 to TABnCCR3) If D0 is set to the TABnCCR0 register and Dk to the TABnCCRk register, the cycle and active level of the PWM waveform are as follows. Cycle = (D0 + 1) × Count clock cycle Active level width = Dk × Count clock cycle Remarks 1.
PAGE 397
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (1) Operation flow in PWM output mode Figure 8-27.
PAGE 398
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 8-27.
PAGE 399
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (2) PWM output mode operation timing (a) Changing pulse width during operation To change the PWM waveform while the counter is operating, write the TABnCCR1 register last. Rewrite the TABnCCRk register after writing the TABnCCR1 register after the INTTABnCC1 signal is detected.
PAGE 400
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) To transfer data from the TABnCCRm register to the CCRm buffer register, the TABnCCR1 register must be written. To change both the cycle and active level of the PWM waveform at this time, first set the cycle to the TABnCCR0 register, set the active level width to the TABnCCR2 and TABnCCR3 registers, and then set the active level width to the TABnCCR1 register.
PAGE 401
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TABnCCRk register to 0000H. If the set value of the TABnCCR0 register is FFFFH, the INTTABnCCk signal is generated periodically.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (c) Generation timing of compare match interrupt request signal (INTTABnCCk) The timing of generation of the INTTABnCCk signal in the PWM output mode differs from the timing of other INTTABnCCk signals; the INTTABnCCk signal is generated when the count value of the 16-bit counter matches the value of the TABnCCRk register.
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V850ES/JG3-H, V850ES/JH3-H 8.5.6 CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) Free-running timer mode (TABnMD2 to TABnMD0 bits = 101) In the free-running timer mode, TABn starts counting when the TABnCTL0.TABnCE bit is set to 1. At this time, the TABnCCRm register can be used as a compare register or a capture register, according to the setting of the TABnOPT0.TABnCCS0 and TABnOPT0.TABnCCS1 bits. Remark m = 0 to 3, n = 0, 1 Figure 8-28.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) When the TABnCE bit is set to 1, TABn starts counting, and the output signals of the TOABn0 to TOABn3 pins are inverted. When the count value of the 16-bit counter subsequently matches the set value of the TABnCCRm register, a compare match interrupt request signal (INTTABnCCm) is generated, and the output signal of the TOABnm pin is inverted. The 16-bit counter continues counting in synchronization with the count clock.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) When the TABnCE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIABnm pin is detected, the count value of the 16-bit counter is stored in the TABnCCRm register, and a capture interrupt request signal (INTTABnCCm) is generated. The 16-bit counter continues counting in synchronization with the count clock.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 8-31. Register Setting in Free-Running Timer Mode (1/3) (a) TABn control register 0 (TABnCTL0) TABnCE TABnCTL0 0/1 TABnCKS2 TABnCKS1 TABnCKS0 0 0 0 0 0/1 0/1 0/1 Select count clockNote 0: Stop counting 1: Enable counting Note The setting is invalid when the TABnCTL1.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 8-31.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 8-31. Register Setting in Free-Running Timer Mode (3/3) (h) TABn capture/compare registers 0 to 3 (TABnCCR0 to TABnCCR3) These registers function as capture registers or compare registers according to the setting of the TABnOPT0.TABnCCSm bit. When the registers function as capture registers, they store the count value of the 16-bit counter when the valid edge input to the TIABnm pin is detected.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (1) Operation flow in free-running timer mode (a) When using capture/compare register as compare register Figure 8-32.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 8-32. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2) <1> Count operation start flow START Register initial setting TABnCTL0 register (TABnCKS0 to TABnCKS2 bits), TABnCTL1 register, TABnIOC0 register, TABnIOC2 register, TABnOPT0 register, TABnCCR0 to TABnCCR3 registers TABnCE bit = 1 The initial setting of these registers is performed before setting the TABnCE bit to 1.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (b) When using capture/compare register as capture register Figure 8-33.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 8-33. Software Processing Flow in Free-Running Timer Mode (Capture Function) (2/2) <1> Count operation start flow START Register initial setting TABnCTL0 register (TABnCKS0 to TABnCKS2 bits), TABnCTL1 register, TABnIOC1 register, TABnOPT0 register TABnCE bit = 1 The initial setting of these registers is performed before setting the TABnCE bit to 1.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (2) Operation timing in free-running timer mode (a) Interval operation with compare register When TABn is used as an interval timer with the TABnCCRm register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the INTTABnCCm signal has been detected.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) When performing an interval operation in the free-running timer mode, four intervals can be set with one channel. To perform the interval operation, the value of the corresponding TABnCCRm register must be re-set in the interrupt servicing that is executed when the INTTABnCCm signal is detected. The set value for re-setting the TABnCCRm register can be calculated by the following expression, where “Dm” is the interval period.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (b) Pulse width measurement with capture register When pulse width measurement is performed with the TABnCCRm register used as a capture register, software processing is necessary for reading the capture register each time the INTTABnCCm signal has been detected and for calculating an interval.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) When executing pulse width measurement in the free-running timer mode, four pulse widths can be measured with one channel. To measure a pulse width, the pulse width can be calculated by reading the value of the TABnCCRm register in synchronization with the INTTABnCCm signal, and calculating the difference between the value read this time and the previously read value. Remark m = 0 to 3, n = 0, 1 R01UH0042EJ0500 Rev.5.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (c) Processing of overflow when two or more capture registers are used Care must be exercised in processing the overflow flag when two or more capture registers are used. First, an example of incorrect processing is shown below.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (1/2) Example when two capture registers are used (using overflow interrupt) FFFFH D11 D10 16-bit counter D01 D00 0000H TABnCE bit INTTABnOV signal TABnOVF bit TABnOVF0 flagNote TIABn0 pin input D01 D00 TABnCCR0 register TABnOVF1 flagNote TIABn1 pin input D11 D10 TABnCCR1 register <1> <2> <3> <4> <5> <6> Note The TABnOVF0 and TABnOVF1 flags are set in the internal RAM by software.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (2/2) Example when two capture registers are used (without using overflow interrupt) FFFFH D11 D10 16-bit counter D01 D00 0000H TABnCE bit INTTABnOV signal TABnOVF bit TABnOVF0 flagNote TIABn0 pin input D01 D00 TABnCCR0 register TABnOVF1 flagNote TIABn1 pin input D11 D10 TABnCCR1 register <1> <2> <3> <4> <5> <6> Note The TABnOVF0 and TABnOVF1 flags are set in the internal RAM by software.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (d) Processing of overflow if capture trigger interval is long If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once from the first capture trigger to the next. First, an example of incorrect processing is shown below.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) Example when capture trigger interval is long FFFFH Dm0 16-bit counter Dm1 0000H TABnCE bit TIABnm pin input TABnCCRm register Dm0 Dm1 INTTABnOV signal TABnOVF bit Overflow counterNote 0H 1H 2H 0H 1 cycle of 16-bit counter Pulse width <1> <2> <3> <4> Note The overflow counter is set arbitrarily by software in the internal RAM. <1> Read the TABnCCRm register (setting of the default value of the TIABnm pin input).
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (e) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TABnOVF bit to 0 with the CLR instruction and by writing 8-bit data (bit 0 is 0) to the TABnOPT0 register. To accurately detect an overflow, read the TABnOVF bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction.
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V850ES/JG3-H, V850ES/JH3-H 8.5.7 CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) Pulse width measurement mode (TABnMD2 to TABnMD0 bits = 110) In the pulse width measurement mode, TABn starts counting when the TABnCTL0.TABnCE bit is set to 1. Each time the valid edge input to the TIABnm pin has been detected, the count value of the 16-bit counter is stored in the TABnCCRm register, and the 16-bit counter is cleared to 0000H.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 8-35. Basic Timing in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TABnCE bit TIABnm pin input TABnCCRm register 0000H D0 D1 D2 D3 INTTABnCCm signal INTTABnOV signal TABnOVF bit Remark Cleared to 0 by CLR instruction m = 0 to 3, n = 0, 1 When the TABnCE bit is set to 1, the 16-bit counter starts counting.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 8-36. Register Setting in Pulse Width Measurement Mode (1/2) (a) TABn control register 0 (TABnCTL0) TABnCE TABnCTL0 0/1 TABnCKS2 TABnCKS1 TABnCKS0 0 0 0 0 0/1 0/1 0/1 Select count clockNote 0: Stop counting 1: Enable counting Note The setting is invalid when the TABnEEE bit = 1.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 8-36. Register Setting in Pulse Width Measurement Mode (2/2) (e) TABn option register 0 (TABnOPT0) TABnOVF TABnCCS3 TABnCCS2 TABnCCS1 TABnCCS0 TABnOPT0 0 0 0 0 0 0 0 0/1 Overflow flag (f) TABn counter read buffer register (TABnCNT) The value of the 16-bit counter can be read by reading the TABnCNT register.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (1) Operation flow in pulse width measurement mode Figure 8-37.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) (2) Operation timing in pulse width measurement mode (a) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TABnOVF bit to 0 with the CLR instruction and by writing 8-bit data (bit 0 is 0) to the TABnOPT0 register. To accurately detect an overflow, read the TABnOVF bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction.
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V850ES/JG3-H, V850ES/JH3-H 8.5.8 CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) Triangular wave PWM mode (TABnMD2 to TABnMD0 bits = 111) In the triangular wave PWM mode, TABn capture/compare register k (TABnCCRk) is used to set the duty factor, and TABn capture/compare register 0 (TABnCCR0) is used to set the cycle. By using these four registers and operating the timer, triangular wave PWM with a variable cycle is output. The value of the TABnCCRm register can be rewritten when TABnCE = 1.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 8-38.
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V850ES/JG3-H, V850ES/JH3-H 8.5.9 CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) Timer output operations The following table shows the operations and output levels of the TOABn0 to TOABn3 pins. Table 8-6.
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V850ES/JG3-H, V850ES/JH3-H 8.6 CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) Timer-Tuned Operation Function/Simultaneous-Start Function Timer AA and timer AB have a timer-tuned operation function/simultaneous-start function. The timers that can be synchronized are listed in Table 8-8. Table 8-8. Timer-Tuned Operation Mode Master Timer Slave Timer TAA1 TAA0 TAA3 TAA2 TAB0 TAA5 For details of the timer-tuned operation function, see 7.
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V850ES/JG3-H, V850ES/JH3-H 8.7 CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) Cautions (1) Capture operation When the capture operation is used and a slow clock is selected as the count clock, FFFFH, not 0000H, may be captured in the TABnCCR0, TABnCCR1, TABnCCR2, and TABnCCR3 registers if the capture trigger is input immediately after the TABnCE bit is set to 1.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Timer T (TMT) is a 16-bit timer/event counter. An encoder count function and other functions are added to timer AA (TAA). However, TMT does not have a function to operate with an external event count input when it operates in the interval timer mode. The V850ES/JG3-H and V850ES/JH3-H have one TMT channel. 9.1 Overview An overview of TMT0 is given below.
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V850ES/JG3-H, V850ES/JH3-H 9.3 CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Configuration TMT0 includes the following hardware. Table 9-1.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 9-1.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (1) 16-bit counter This 16-bit counter can count internal clocks or external events. The count value of this counter can be read by using the TT0CNT register. When the TT0CTL0.TT0CE bit = 0, the value of the 16-bit counter is FFFFH. If the TT0CNT register is read at this time, 0000H is read. Reset sets the TT0CE bit to 0. (2) CCR0 buffer register This is a 16-bit compare register that compares the count value of the 16-bit counter.
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V850ES/JG3-H, V850ES/JH3-H 9.3.1 CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Pin configuration The timer inputs and outputs that configure TMT0 are shared with the following ports. The port functions must be set when using each pin (see Table 4-20 Using Port Pin as Alternate-Function Pin). Table 9-2.
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V850ES/JG3-H, V850ES/JH3-H 9.4 CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Registers (1) TMT0 control register 0 (TT0CTL0) The TT0CTL0 register is an 8-bit register that controls the operation of TMT0. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. The same value can always be written to the TT0CTL0 register by software.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (2) TMT0 control register 1 (TT0CTL1) The TT0CTL1 register is an 8-bit register that controls the TMT0 operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. (1/2) After reset: 00H TT0CTL1 R/W Address: FFFFF601H 7 6 5 4 0 TT0EST TT0EEE 0 3 1 0 Software trigger control TT0EST − 0 1 2 TT0MD3 TT0MD2 TT0MD1 TT0MD0 Generates a valid signal for external trigger input.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (2/2) Cautions 1. The TT0EST bit is valid only in the external trigger pulse output mode or one-shot pulse output mode. In any other mode, writing 1 to this bit is ignored. 2. The TT0EEE bit is valid only in the interval timer mode, external trigger pulse output mode, one-shot pulse output mode, PWM output mode, free-running timer mode, pulse width measurement mode, or triangular-wave PWM output mode.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (3) TMT0 control register 2 (TT0CTL2) The TT0CTL2 register is an 8-bit register that controls the encoder count function operation. The TT0CTL2 register is valid only in the encoder compare mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. Caution For details of each bit of the TT0CTL2 register, see 9.6.9 (5) Controlling bits of TT0CTL2 register.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (2/2) Up/down count selection TT0UDS1 TT0UDS0 0 0 When valid edge of TENC00 input is detected Counts down when TENC01 = high level. Counts up when TENC01 = low level. 0 1 1 0 Counts up when valid edge of TENC00 input is detected. Counts down when valid edge of TENC01 input is detected. Counts down when rising edge of TENC00 input is detected. Counts up when falling edge of TENC00 input is detected.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (4) TMT0 I/O control register 0 (TT0IOC0) The TT0IOC0 register is an 8-bit register that controls the timer output (TOT00, TOT01 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. R01UH0042EJ0500 Rev.5.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) After reset: 00H TT0IOC0 R/W Address: FFFFF603H 7 6 5 4 0 0 0 0 3 <2> TT0OL1 TT0OE1 1 <0> TT0OL0 TT0OE0 TOT01 pin output level settingNote TT0OL1 0 TOT01 pin starts output at high level. 1 TOT01 pin starts output at low level. TT0OE1 TOT01 pin output setting 0 Timer output prohibited • Low level is output from the TOT01 pin when the TT0OL1 bit = 0.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (5) TMT0 I/O control register 1 (TT0IOC1) The TT0IOC1 register is an 8-bit register that controls the valid edge for the capture trigger input signals (TIT00, TIT01 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (6) TMT0 I/O control register 2 (TT0IOC2) The TT0IOC2 register is an 8-bit register that controls the valid edge for the external event count input signal (EVTT0 pin) and external trigger input signal (EVTT0 pin). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (7) TMT0 I/O control register 3 (TT0IOC3) The TT0IOC3 register is an 8-bit register that controls the encoder clear function operation. The TT0IOC3 register is valid only in the encoder compare mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (2/2) TT0ECS1 TT0ECS0 Valid edge setting of encoder clear signal (TECR0 pin) 0 0 Detects no edge (clearing encoder is invalid). 0 1 Detects rising edge. 1 0 Detects falling edge. 1 1 Detects both edges. TT0EIS1 TT0EIS0 Valid edge setting of encoder input signals (TENC00, TENC01 pins) 0 0 Detects no edge (inputting encoder is invalid). 0 1 Detects rising edge. 1 0 Detects falling edge. 1 1 Detects both edges.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (8) TMT0 option register 0 (TT0OPT0) The TT0OPT0 register is an 8-bit register that sets the capture/compare operation and detects overflows. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (9) TMT0 option register 1 (TT0OPT1) The TT0OPT1 register is an 8-bit register that detects overflows, underflows, and count-up/down operations of the encoder count function. The TT0OPT1 register is valid only in the encoder compare mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. This register can be rewritten even when the TT0CTL0.TT0CE bit = 1.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (2/2) TT0EOF Set (1) Overflow detection flag for TMT0 encoder function Overflow occurs. Reset (0) Cleared by writing 0 to the TT0EOF bit or when the TT0CTL0.TT0CE bit = 0 • The TT0EOF bit is set to 1 when the 16-bit counter overflows from FFFFH to 0000H in the encoder compare mode. • As soon as the TT0EOF bit has been set to 1, an overflow interrupt request signal (INTTTOV0) is generated. At this time, the TT0OPT0.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (10) TMT0 capture/compare register 0 (TT0CCR0) The TT0CCR0 register is a 16-bit register that can be used as a capture register or compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TT0OPT0.TT0CCS0 bit. In the pulse width measurement mode, the TT0CCR0 register can be used only as a capture register.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (a) Function as compare register The TT0CCR0 register can be rewritten even when the TT0CTL0.TT0CE bit = 1. The set value of the TT0CCR0 register is transferred to the CCR0 buffer register. When the value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTT0CC0) is generated. If TOT00 pin output is enabled at this time, the output of the TOT00 pin is inverted.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (11) TMT0 capture/compare register 1 (TT0CCR1) The TT0CCR1 register is a 16-bit register that can be used as a capture register or compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TT0OPT0.TT0CCS1 bit. In the pulse width measurement mode, the TT0CCR1 register can be used only as a capture register.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (a) Function as compare register The TT0CCR1 register can be rewritten even when the TT0CTL0.TT0CE bit = 1. The set value of the TT0CCR1 register is transferred to the CCR1 buffer register. When the value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTT0CC01) is generated. If TOT01 pin output is enabled at this time, the output of the TOT01 pin is inverted.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (12) TMT0 counter write register (TT0TCW) The TT0TCW register is used to set the initial value of the 16-bit counter. The TT0TCW register is valid only in the encoder compare mode. This register can be read or written in 16-bit units. Rewrite the TT0TCW register when the TT0CTL0.TT0CE bit = 0. The value of the TT0TCW register is transferred to the 16-bit counter when the TT0CE bit is set (1). Reset sets this register to 0000H.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (14) Noise elimination control register (TTNFC) Digital noise elimination can be selected for the TIT00, TIT01, TENC01, TECR0, and EVTT00 pins. The noise elimination settings are performed using the TTNFC register. When digital noise elimination is selected, the sampling clock for digital sampling can be selected from among fXX, fXX/4, fXX/8, fXX/16, fXX/32, and fXX/64. Sampling is performed 3 times.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) A timing example of noise elimination performed by the timer T input pin digital filter is shown Figure 9-2. Figure 9-2.
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V850ES/JG3-H, V850ES/JH3-H 9.5 CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Timer Output Operations The following table shows the operations and output levels of the TOT00 and TOT01 pins. Table 9-5.
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V850ES/JG3-H, V850ES/JH3-H 9.6 CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Operation The functions of TMT0 that can be implemented differ from one channel to another. The functions of each channel are shown below. Table 9-7. TMT0 Specifications in Each Mode Operation TT0CTL1.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (1) Basic counter operation This section explains the basic operation of the 16-bit counter. For details, refer to the description of the operation in each mode. (a) Count start operation • Encoder compare mode A count operation is controlled by TENC00 and TENC01 phases. The 16-bit counter initial setting is performed by transferring the set value of the TT0TCW register to the 16bit counter and the count operation is started.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (d) Count value hold operation The value of the 16-bit counter is held by the TT0CTL2.TT0ECC bit in the encoder compare mode. The value of the 16-bit counter is reset to FFFFH when the TT0ECC bit = 0 and TT0CTL0.TT0CE bit = 0. When the TT0CE bit is next set to 1, the set value of the TT0TCW register is transferred to the 16-bit counter and a count operation is performed.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (2) Anytime write and batch write The TT0CCR0 and TT0CCR1 registers in TMT0 can be rewritten during timer operation (TT0CTL0.TT0CE bit = 1), but the write method (anytime write, batch write) of the CCR0 and CCR1 buffer registers differs depending on the mode. (a) Anytime write In this mode, data is transferred at any time from the TT0CCR0 and TT0CCR1 registers to the CCR0 and CCR1 buffer registers during timer operation (n = 0, 1).
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 9-4. Timing of Anytime Write TT0CE bit = 1 D01 FFFFH D01 D02 16-bit counter D11 D11 D12 D12 0000H D01 TT0CCR0 register CCR0 buffer register 0000H D01 D11 TT0CCR1 register CCR1 buffer register D02 0000H D02 D12 D11 D12 INTTT0CC0 signal INTTT0CC1 signal Remarks 1. D01, D02: Set values of TT0CCR0 register D11, D12: Set values of TT0CCR1 register 2.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (b) Batch write In this mode, data is transferred all at once from the TT0CCR0 and TT0CCR1 registers to the CCR0 and CCR1 buffer registers during timer operation. This data is transferred upon a match between the value of the CCR0 buffer register and the value of the 16-bit counter. Transfer is enabled by writing to the TT0CCR1 register.
PAGE 467
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 9-5.
PAGE 468
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 9-6. Timing of Batch Write TT0CE bit = 1 D01 FFFFH D02 D11 D12 16-bit counter D03 D02 D12 D12 D12 0000H TT0CCR0 register D01 CCR0 buffer register 0000H TT0CCR1 register D02 D01 D11 CCR1 buffer register 0000H D03 D02 Note 1 Note 2 D12 D11 D12 Note 1 Note 1 Same value write D12 Note 3 D03 D12 Note 1 INTTT0CC0 signal INTTT0CC1 signal TOT00 pin output TOT01 pin output Notes 1.
PAGE 469
V850ES/JG3-H, V850ES/JH3-H 9.6.1 CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Interval timer mode (TT0MD3 to TT0MD0 bits = 0000) In the interval timer mode, an interrupt request signal (INTTT0CC0) is generated at the interval set by the TT0CCR0 register if the TT0CTL0.TT0CE bit is set to 1. A square wave whose half cycle is equal to the interval can be output from the TOT00 pin. The TT0CCR1 register is not used in the interval timer mode.
PAGE 470
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) When the TT0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts counting. At this time, the output of the TOT00 pin is inverted. Additionally, the set value of the TT0CCR0 register is transferred to the CCR0 buffer register.
PAGE 471
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 9-9. Register Setting for Interval Timer Mode Operation (2/2) (d) TMT0 counter read buffer register (TT0CNT) By reading the TT0CNT register, the count value of the 16-bit counter can be read. (e) TMT0 capture/compare register 0 (TT0CCR0) If the TT0CCR0 register is set to D0, the interval is as follows.
PAGE 472
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (1) Interval timer mode operation flow Figure 9-10.
PAGE 473
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (2) Interval timer mode operation timing (a) Operation if TT0CCR0 register is set to 0000H If the TT0CCR0 register is set to 0000H, the INTTT0CC0 signal is generated at each count clock, and the output of the TOT00 pin is inverted. The value of the 16-bit counter is always 0000H.
PAGE 474
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (b) Operation if TT0CCR0 register is set to FFFFH If the TT0CCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH. The counter is cleared to 0000H in synchronization with the next count-up timing. The INTTT0CC0 signal is generated and the output of the TOT00 pin is inverted. At this time, an overflow interrupt request signal (INTTT0OV) is not generated, nor is the overflow flag (TT0OPT0.TT0OVF bit) set to 1.
PAGE 475
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (c) Notes on rewriting TT0CCR0 register If the value of the TT0CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. When an overflow may occur, stop counting and then change the set value.
PAGE 476
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (d) Operation of TT0CCR1 register Figure 9-11. Configuration of TT0CCR1 Register TT0CCR1 register CCR1 buffer register Output controller Match signal TOT01 pin INTTT0CC1 signal Clear Count clock selection 16-bit counter Match signal TT0CE bit Output controller TOT00 pin INTTT0CC0 signal CCR0 buffer register TT0CCR0 register R01UH0042EJ0500 Rev.5.
PAGE 477
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) When the TT0CCR1 register is set to the same value as the TT0CCR0 register, the INTTT0CC0 signal is generated at the same timing as the INTTT0CC1 signal and the TOT01 pin output is inverted. In other words, a square wave can be output from the TOT01 pin. The following shows the operation when the TT0CCR1 register is set to other than the value set in the TT0CCR0 register.
PAGE 478
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) If the set value of the TT0CCR1 register is greater than the set value of the TT0CCR0 register, the count value of the 16-bit counter does not match the value of the TT0CCR1 register. Consequently, the INTTT0CC1 signal is not generated, nor is the output of the TOT01 pin changed. When the TT0CCR1 register is not used, it is recommended to set its value to FFFFH. Figure 9-13.
PAGE 479
V850ES/JG3-H, V850ES/JH3-H 9.6.2 CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) External event count mode (TT0MD3 to TT0MD0 bits = 0001) In the external event count mode, the valid edge of the external event count input (EVTT0) is counted when the TT0CTL0.TT0CE bit is set to 1, and an interrupt request signal (INTTT0CC0) is generated each time the number of edges set by the TT0CCR0 register have been counted. The TOT00 and TOT01 pins cannot be used.
PAGE 480
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 9-15.
PAGE 481
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) When the TT0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts each time the valid edge of external event count input is detected. Additionally, the set value of the TT0CCR0 register is transferred to the CCR0 buffer register.
PAGE 482
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 9-16. Register Setting for Operation in External Event Count Mode (2/2) (f) TMT0 capture/compare register 1 (TT0CCR1) The TT0CCR1 register is not used in the external event count mode. However, the set value of the TT0CCR1 register is transferred to the CCR1 buffer register.
PAGE 483
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (1) External event count mode operation flow Figure 9-17. Software Processing Flow in External Event Count Mode FFFFH D0 16-bit counter D0 D0 0000H TT0CE bit TT0CCR0 register D0 INTTT0CC0 signal <1> <2> <1> Count operation start flow START Register initial setting TT0CTL1 register, TT0IOC2 register, TT0CCR0, TT0CCR1 registers Initial setting of these registers is performed before setting the TT0CE bit to 1.
PAGE 484
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (2) Operation timing in external event count mode (a) Operation if TT0CCR0 register is set to 0000H When the TT0CCR0 register is set to 0000H, the 16-bit counter is repeatedly cleared to 0000H and generates the INTTT0CC0 signal each time it has detected the valid edge of the external event count signal and its value has matched that of the CCR0 buffer register. The value of the 16-bit counter is always 0000H.
PAGE 485
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (c) Operation with TT0CCR0 set to FFFFH and TT0CCR1 register to 0000H When the TT0CCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH each time it has detected the valid edge of the external event count signal. The counter is then cleared to 0000H in synchronization with the next count-up timing and the INTTT0CC0 signal is generated. At this time, the TT0OPT0.TT0OVF bit is not set.
PAGE 486
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (d) Notes on rewriting TT0CCR0 register If the value of the TT0CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. When an overflow may occur, stop counting once and then change the set value.
PAGE 487
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (e) Operation of TT0CCR1 register Figure 9-18. Configuration of TT0CCR1 Register TT0CCR1 register CCR1 buffer register Match signal INTTT0CC1 signal Clear EVTT0 pin (external event count input) Edge detectorNote 16-bit counter Match signal TT0CE bit INTTT0CC0 signal CCR0 buffer register TT0CCR0 register Note Set by the TT0IOC2.TT0EES1 and TT0IOC2.TT0EES0 bits.
PAGE 488
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) If the set value of the TT0CCR1 register is greater than the set value of the TT0CCR0 register, the INTTT0CC1 signal is not generated because the count value of the 16-bit counter and the value of the TT0CCR1 register do not match. When the TT0CCR1 register is not used, it is recommended to set its value to FFFFH. Figure 9-20.
PAGE 489
V850ES/JG3-H, V850ES/JH3-H 9.6.3 CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) External trigger pulse output mode (TT0MD3 to TT0MD0 bits = 0010) In the external trigger pulse output mode, 16-bit timer/event counter T waits for a trigger when the TT0CTL0.TT0CE bit is set to 1. When the valid edge of an external trigger input (EVTT0) is detected, 16-bit timer/event counter T starts counting, and outputs a PWM waveform from the TOT01 pin.
PAGE 490
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 9-22.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 9-23. Setting of Registers in External Trigger Pulse Output Mode (1/2) (a) TMT0 control register 0 (TT0CTL0) TT0CE TT0CTL0 TT0CKS2 TT0CKS1 TT0CKS0 0/1 0 0 0 0 0/1 0/1 0/1 Select count clock 0: Stops counting 1: Enables counting Note The setting is invalid when the TT0CTL1.TT0EEE bit = 1.
PAGE 492
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 9-23. Setting of Registers in External Trigger Pulse Output Mode (2/2) (d) TMT0 I/O control register 2 (TT0IOC2) TT0EES1 TT0EES0 TT0ETS1 TT0ETS0 TT0IOC2 0 0 0 0 0 0 0/1 0/1 Select valid edge of external trigger input (EVTT0 pin)Note Note Set the valid edge selection of the unused alternate external input signals to “No edge detection”.
PAGE 493
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (1) Operation flow in external trigger pulse output mode Figure 9-24.
PAGE 494
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 9-24.
PAGE 495
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (2) External trigger pulse output mode operation timing (a) Note on changing pulse width during operation To change the PWM waveform while the counter is operating, write the TT0CCR1 register last. Rewrite the TT0CCRn register after writing the TT0CCR1 register after the INTTT0CC0 signal is detected.
PAGE 496
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) In order to transfer data from the TT0CCRn register to the CCRn buffer register, the TT0CCR1 register must be written. To change both the cycle and active level width of the PWM waveform at this time, first set the cycle to the TT0CCR0 register and then set the active level width to the TT0CCR1 register.
PAGE 497
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TT0CCR1 register to 0000H. The 16-bit counter is cleared to 0000H and the INTTT0CC0 and INTTT0CC1 signals are generated after a match between the count value of the 16-bit counter and the value of the CCR0 buffer register.
PAGE 498
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) To output a 100% waveform, set a value of (set value of TT0CCR0 register + 1) to the TT0CCR1 register. If the set value of the TT0CCR0 register is FFFFH, 100% output cannot be produced.
PAGE 499
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (c) Conflict between trigger detection and match with CCR1 buffer register If the trigger is detected immediately after the INTTT0CC1 signal is generated, the 16-bit counter is immediately cleared to 0000H, the TOT01 pin is asserted, and the counter continues counting. Consequently, the inactive period of the PWM waveform is shortened.
PAGE 500
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (d) Conflict between trigger detection and match with CCR0 buffer register If the trigger is detected immediately after the INTTT0CC0 signal is generated, the 16-bit counter is cleared to 0000H and continues counting up again from that point. Therefore, the active period of the TOT01 pin is extended by the time from generation of the INTTT0CC0 signal to trigger detection.
PAGE 501
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (e) Generation timing of compare match interrupt request signal (INTTT0CC1) The timing of generating the INTTT0CC1 signal in the external trigger pulse output mode differs from the timing of generating INTTT0CC1 signals in other modes; the INTTT0CC1 signal is generated when the count value of the 16-bit counter matches the value of the TT0CCR1 register.
PAGE 502
V850ES/JG3-H, V850ES/JH3-H 9.6.4 CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) One-shot pulse output mode (TT0MD3 to TT0MD0 bits = 0011) In the one-shot pulse output mode, 16-bit timer/event counter T waits for a trigger when the TT0CTL0.TT0CE bit is set to 1. When the valid edge of an external trigger input (EVTT0) is detected, 16-bit timer/event counter T starts counting, and outputs a one-shot pulse from the TOT01 pin.
PAGE 503
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 9-26.
PAGE 504
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 9-27.
PAGE 505
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 9-27. Setting of Registers in One-Shot Pulse Output Mode (2/2) (d) TMT0 I/O control register 2 (TT0IOC2) TT0EES1 TT0EES0 TT0ETS1 TT0ETS0 TT0IOC2 0 0 0 0 0 0 0/1 0/1 Select valid edge of external trigger input (EVTT0 pin)Note Note Set the valid edge selection of the unused alternate external input signals to “No edge detection”.
PAGE 506
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (1) Operation flow in one-shot pulse output mode Figure 9-28.
PAGE 507
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (2) Operation timing in one-shot pulse output mode (a) Note on rewriting TT0CCRn register If the value of the TT0CCRn register is rewritten to a smaller value during counting, the 16-bit counter may overflow. When an overflow may occur, stop counting and then change the set value.
PAGE 508
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (b) Generation timing of compare match interrupt request signal (INTTT0CC1) The generation timing of the INTTT0CC1 signal in the one-shot pulse output mode is different from INTTT0CC1 signals in other modes; the INTTT0CC1 signal is generated when the count value of the 16-bit counter matches the value of the TT0CCR1 register.
PAGE 509
V850ES/JG3-H, V850ES/JH3-H 9.6.5 CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) PWM output mode (TT0MD3 to TT0MD0 bits = 0100) In the PWM output mode, a PWM waveform is output from the TOT01 pin when the TT0CTL0.TT0CE bit is set to 1. In addition, a square wave with the set value of the TT0CCR0 register + 1 as half its cycle is output from the TOT00 pin. Figure 9-29.
PAGE 510
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 9-30.
PAGE 511
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 9-31. Setting of Registers in PWM Output Mode (1/2) (a) TMT0 control register 0 (TT0CTL0) TT0CE TT0CTL0 TT0CKS2 TT0CKS1 TT0CKS0 0/1 0 0 0 0 0/1 0/1 0/1 Select count clockNote 0: Stops counting 1: Enables counting Note The setting is invalid when the TT0CTL1.TT0EEE bit = 1.
PAGE 512
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 9-31. Register Setting in PWM Output Mode (2/2) (d) TMT0 I/O control register 2 (TT0IOC2) TT0EES1 TT0EES0 TT0ETS1 TT0ETS0 TT0IOC2 0 0 0 0 0/1 0/1 0 0 Select valid edge of external event count input (EVTT0 pin). (e) TMT0 counter read buffer register (TT0CNT) The value of the 16-bit counter can be read by reading the TT0CNT register.
PAGE 513
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (1) Operation flow in PWM output mode Figure 9-32. Software Processing Flow in PWM Output Mode (1/2) FFFFH D01 16-bit counter D00 D01 D00 D10 D10 D01 D11 D11 D10 D00 D10 0000H TT0CE bit TT0CCR0 register D00 CCR0 buffer register D01 D00 D00 D01 D00 INTTT0CC0 signal TOT00 pin output D10 TT0CCR1 register D10 D10 CCR1 buffer register D11 D10 D10 D11 D10 INTTT0CC1 signal TOT01 pin output <1> R01UH0042EJ0500 Rev.
PAGE 514
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 9-32.
PAGE 515
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (2) PWM output mode operation timing (a) Changing pulse width during operation To change the PWM waveform while the counter is operating, write the TT0CCR1 register last. Rewrite the TT0CCRn register after writing the TT0CCR1 register after the INTTT0CC1 signal is detected.
PAGE 516
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TT0CCR1 register to 0000H. The 16-bit counter is cleared to 0000H and the INTTT0CC0 and INTTT0CC1 signals are generated after a match between the count value of the 16-bit counter and the value of the CCR0 buffer register.
PAGE 517
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (c) Generation timing of compare match interrupt request signal (INTTT0CC1) The timing of generation of the INTTT0CC1 signal in the PWM output mode differs from the timing of INTTT0CC1 signals in other modes; the INTTT0CC1 signal is generated when the count value of the 16-bit counter matches the value of the TT0CCR1 register.
PAGE 518
V850ES/JG3-H, V850ES/JH3-H 9.6.6 CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Free-running timer mode (TT0MD3 to TT0MD0 bits = 0101) In the free-running timer mode, 16-bit timer/event counter T starts counting when the TT0CTL0.TT0CE bit is set to 1. At this time, the TT0CCR0 and TT0CCR1 registers can be used as compare registers or capture registers, depending on the setting of the TT0OPT0.TT0CCS0 and TT0OPT0.TT0CCS1 bits. Figure 9-33.
PAGE 519
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) • Compare operation When the TT0CE bit is set to 1, 16-bit timer/event counter T starts counting, and the output signal of the TOT0n pin is inverted. When the count value of the 16-bit counter later matches the set value of the TT0CCRn register, a compare match interrupt request signal (INTTT0CCn) is generated, and the output signal of the TOT0n pin is inverted.
PAGE 520
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) • Capture operation When the TT0CE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIT0n pin is detected, the count value of the 16-bit counter is stored in the TT0CCRn register, and a capture interrupt request signal (INTTT0CCn) is generated. The 16-bit counter continues counting in synchronization with the count clock.
PAGE 521
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 9-36. Register Setting in Free-Running Timer Mode (1/2) (a) TMT0 control register 0 (TT0CTL0) TT0CE TT0CTL0 TT0CKS2 TT0CKS1 TT0CKS0 0/1 0 0 0 0 0/1 0/1 0/1 Select count clockNote 0: Stops counting 1: Enables counting Note The setting is invalid when the TT0CTL1.
PAGE 522
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 9-36.
PAGE 523
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (1) Operation flow in free-running timer mode (a) When using capture/compare register as compare register Figure 9-37.
PAGE 524
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 9-37. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2) <1> Count operation start flow START Register initial setting TT0CTL0 register (TT0CKS0 to TT0CKS2 bits) TT0CTL1 register, TT0IOC0 register, TT0IOC2 register, TT0OPT0 register, TT0CCR0 register, TT0CCR1 register Initial setting of these registers is performed before setting the TT0CE bit to 1.
PAGE 525
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (b) When using capture/compare register as capture register Figure 9-38.
PAGE 526
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 9-38. Software Processing Flow in Free-Running Timer Mode (Capture Function) (2/2) <1> Count operation start flow START Register initial setting TT0CTL0 register (TT0CKS0 to TT0CKS2 bits) TT0CTL1 register, TT0IOC1 register, TT0OPT0 register Initial setting of these registers is performed before setting the TT0CE bit to 1. The TT0CKS0 to TT0CKS2 bits can be set at the same time as when counting starts (TT0CE bit = 1).
PAGE 527
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (2) Operation timing in free-running timer mode (a) Interval operation with compare register When 16-bit timer/event counter T is used as an interval timer with the TT0CCRn register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the INTTT0CCn signal has been detected.
PAGE 528
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (b) Pulse width measurement with capture register When pulse width measurement is performed with the TT0CCRn register used as a capture register, software processing is necessary for reading the capture register each time the INTTT0CCn signal has been detected and for calculating an interval.
PAGE 529
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (c) Processing of overflow when two capture registers are used Care must be exercised in processing the overflow flag when two capture registers are used. First, an example of incorrect processing is shown below.
PAGE 530
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (1/2) Example when two capture registers are used (using overflow interrupt) FFFFH D11 D10 16-bit counter D01 D00 0000H TT0CE bit INTTT0OV signal TT0OVF bit TT0OVF0 flagNote TIT00 pin input D01 D00 TT0CCR0 register TT0OVF1 flagNote TIT01 pin input D11 D10 TT0CCR1 register <1> <2> <3> <4> <5> <6> Note The TT0OVF0 and TT0OVF1 flags are set on the internal RAM by software.
PAGE 531
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (2/2) Example when two capture registers are used (without using overflow interrupt) FFFFH D11 D10 16-bit counter D01 D00 0000H TT0CE bit INTTT0OV signal TT0OVF bit TT0OVF0 flagNote TIT00 pin input D01 D00 TT0CCR0 register TT0OVF1 flagNote TIT01 pin input D11 D10 TT0CCR1 register <1> <2> <3> <4> <5> <6> Note The TT0OVF0 and TT0OVF1 flags are set on the internal RAM by software.
PAGE 532
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (d) Processing of overflow if capture trigger interval is long If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once from the first capture trigger to the next. First, an example of incorrect processing is shown below.
PAGE 533
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Example when capture trigger interval is long FFFFH Da0 16-bit counter Da1 0000H TT0CE bit TIT0n pin input TT0CCRn register Da0 Da1 INTTT0OV signal TT0OVF bit Overflow counterNote 0H 1H 2H 0H 1 cycle of 16-bit counter Pulse width <1> <2> <3> <4> Note The overflow counter is set arbitrarily by software on the internal RAM. <1> Read the TT0CCRn register (setting of the default value of the TIT0n pin input).
PAGE 534
V850ES/JG3-H, V850ES/JH3-H 9.6.7 CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Pulse width measurement mode (TT0MD3 to TT0MD0 bits = 0110) In the pulse width measurement mode, 16-bit timer/event counter T starts counting when the TT0CTL0.TT0CE bit is set to 1. Each time the valid edge input to the TIT0n pin has been detected, the count value of the 16-bit counter is stored in the TT0CCRn register, and the 16-bit counter is cleared to 0000H.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 9-40. Basic Timing in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TT0CE bit TIT0n pin input TT0CCRn register 0000H D0 D1 D2 D3 INTTT0CCn signal INTTT0OV signal TT0OVF bit Remark Cleared to 0 by CLR instruction n = 0, 1 When the TT0CE bit is set to 1, the 16-bit counter starts counting.
PAGE 536
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 9-41. Register Setting in Pulse Width Measurement Mode (1/2) (a) TMT0 control register 0 (TT0CTL0) TT0CE TT0CTL0 0/1 TT0CKS2 TT0CKS1 TT0CKS0 0 0 0 0 0/1 0/1 0/1 Select count clockNote 0: Stops counting 1: Enables counting Note Setting is invalid when the TT0CTL1.TT0EEE bit = 1.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 9-41. Register Setting in Pulse Width Measurement Mode (2/2) (e) TMT0 option register 0 (TT0OPT0) TT0CCS1 TT0CCS0 TT0OPT0 0 0 0 0 TT0OVF 0 0 0 0/1 Overflow flag (f) TMT0 counter read buffer register (TT0CNT) The value of the 16-bit counter can be read by reading the TT0CNT register.
PAGE 538
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (1) Operation flow in pulse width measurement mode Figure 9-42.
PAGE 539
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (2) Operation timing in pulse width measurement mode (a) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TT0OVF bit to 0 with the CLR instruction after reading the TT0OVF bit when it is 1 and by writing 8-bit data (bit 0 is 0) to the TT0OPT0 register after reading the TT0OVF bit when it is 1. R01UH0042EJ0500 Rev.5.
PAGE 540
V850ES/JG3-H, V850ES/JH3-H 9.6.8 CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Triangular-wave PWM output mode (TT0MD3 to TT0MD0 bits = 0111) In the triangular-wave PWM output mode, a triangular-wave PWM waveform is output from the TOT01 pin when the TT0CTL0.TT0CE bit is set to 1. A PWM waveform that is inverted when the count value of the 16-bit counter matches the value of the CCR0 buffer register and when the 16-bit counter is set to 0000H is output from the TOT00 pin. Figure 9-43.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 9-44.
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V850ES/JG3-H, V850ES/JH3-H 9.6.9 CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Encoder count function The encoder count function includes an encoder compare mode (see 9.6.10 Encoder compare mode (TT0MD3 to TT0MD0 bits = 1000)). Mode Encoder compare mode TT0CCR0 Register Compare only TT0CCR1 Register Compare only (1) Count-up/-down control Counting up or down by the 16-bit counter is controlled by the phase of input encoder signals (TENC00 and TENC01) and settings of the TT0CTL2.TT0UDS1 and TT0CTL2.
PAGE 543
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (5) Controlling bits of TT0CTL2 register The setting of the TT0CTL2 register in the encoder compare mode is shown below. Table 9-8. Setting of TT0CTL2 Register Mode TT0UDS1, TT0ECM1 Bit TT0ECM0 Bit TT0LDE Bit Counter Clear Transfer to TT0UDS0 Bits (<2>) (<2>) (<3>) (Target Compare Counter (<1>) Encoder compare mode Can be set to 00, Register) 0 0 − 0 01, 10, or 11.
PAGE 544
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (b) Detailed explanation of each bit <1> TT0UDS1 and TT0UDS0 bits: Count-up/-down selection Whether the 16-bit counter is counting up or down is identified by the phase input from the TENC00 or TENC01 pin and depending on the settings of the TT0UDS1 and TT0UDS0 bits. These bits are valid only in the encoder compare mode.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) • When TT0UDS1 and TT0UDS0 bits = 01 TENC00 Pin Low level TENC01 Pin Count Operation Count down Rising edge Falling edge Both edges High level Rising edge Falling edge Both edges Rising edge High level Count up Falling edge Both edges Rising edge Low level Falling edge Both edges Counter does not perform count Simultaneous input to TENC00 and TENC01 pins operation but holds value immediately before.
PAGE 546
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) • When TT0UDS1 and TT0UDS0 bits = 10 TENC00 Pin Low level TENC01 Pin Falling edge Count Operation Counter does not perform count operation but holds value immediately before. Rising edge Low level Count down High level Rising edge Counter does not perform count Falling edge High level operation but holds value immediately before.
PAGE 547
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) • When TT0UDS1 and TT0UDS0 bits = 11 TENC00 Pin TENC01 Pin Low level Falling edge Rising edge Low level High level Rising edge Falling edge High level Count Operation Count down Rising edge Count up High level Falling edge Falling edge Low level Low level Rising edge Counter does not perform count Simultaneous input to TENC00 and TENC01 pins operation but holds value immediately before.
PAGE 548
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) <2> TT0ECM1 and TT0ECM0 bits: Timer/counter clear function upon match of the compare register The 16-bit counter performs its count operation in accordance with the set value of the TT0ECM1 and TT0ECM0 bits when the count value of the counter matches the value of the CCRn buffer register. • When TT0ECM1 and TT0ECM0 bits = 00 The 16-bit counter is not cleared when its count value matches the value of the CCRn buffer register.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) <3> TT0LDE bit: Transfer function of the set value of the TT0CCR0 register to the 16-bit counter when the counter underflows When the TT0LDE bit = 1, the set value of the TT0CCR0 register can be transferred to the 16-bit counter when the counter underflows. The TT0LDE bit is valid only in the encoder compare mode.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 9-52.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (6) Function to clear counter to 0000H by encoder clear signal (TECR0 pin) The 16-bit counter can be cleared to 0000H by the input signal of the TECR0 pin in two ways which are selected by the TT0IOC3.TT0SCE bit. The TT0SCE bit also controls, depending on its setting, the TT0IOC3.TT0ZCL, TT0IOC3.TT0BCL, TT0IOC3.TT0ACL, TT0IOC3.TT0ESC1, and TT0IOC3.TT0ECS0 bits.
PAGE 552
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (b) Clearing method <2>: By detecting clear level condition of the TENC00, TENC01, and TECR0 pins (TT0SCE bit = 1) When the TT0SCE bit = 1, the 16-bit counter is cleared to 0000H if the clear level condition of the TECR0, TENC00, or TENC01 pin specified by the TT0ZCL, TT0BCL, and TT0ACL bits is detected. At this time, the encoder clear interrupt request signal (INTTT0EC) is not generated.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 9-54. Operation Example (When TT0SCE Bit = 1, TT0ZCL Bit = 1, TT0BCL Bit = 0, TT0ACL Bit = 1, TT0UDS1 and TT0UDS0 Bits = 11, TECR0 = High Level, TENC01 = Low Level, and TENC00 = High Level) (1/3) (i) If inputting the high level to the TECR0 pin lags behind inputting the low level to the TENC01 pin while the counter is counting up, the counter is cleared after it counts up.
PAGE 554
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 9-54. Operation Example (When TT0SCE Bit = 1, TT0ZCL Bit = 1, TT0BCL Bit = 0, TT0ACL Bit = 1, TT0UDS1 and TT0UDS0 Bits = 11, TECR0 = High Level, TENC01 = Low Level, and TENC00 = High Level) (2/3) (ii) If the high level is input to the TECR0 pin at the same time as the low level is input to the TECN01 pin while the counter is counting up, the counter is cleared without counting up.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 9-54. Operation Example (When TT0SCE Bit = 1, TT0ZCL Bit = 1, TT0BCL Bit = 0, TT0ACL Bit = 1, TT0UDS1 and TT0UDS0 Bits = 11, TECR0 = High Level, TENC01 = Low Level, and TENC00 = High Level) (3/3) (iv) If the high level is input to the TECR0 pin later than the low level is input to the TENC01 pin while the counter is counting up, the counter is cleared after it counts up.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (7) Notes on using encoder count function (a) If compare match interrupt is not generated immediately after operation is started If a value which is the same as that of the TT0TCW register is set to the TT0CCR0 or TT0CCR1 register and the counter operation is started when the TT0CTL2.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (b) If overflow does not occur immediately after start of operation If the count operation is resumed when the TT0CTL2.TT0ECC bit = 1, the 16-bit counter does not overflow if its count value that has been held is FFFFH and if the next count operation is counting up. After the counter starts operating and counts up from a count value (value of TT0TCW register = FFFFH), the counter overflows from FFFFH to 0000H.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) 9.6.10 Encoder compare mode (TT0MD3 to TT0MD0 bits = 1000) In the encoder compare mode, the encoder is controlled by using both the TT0CCR0 and TT0CCR1 registers as compare registers and the input pins for encoder count function (TENC00, TENC01, and TECR0).
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 9-56. Encoder Compare Mode Operation Processing A Valid edge of TENC00, TENC01 detected? No Yes Count down Which count operation? Count up TT0ECM0 = 1? (TT0CTL2) No Yes Count value matches CCR0 register value? TT0ECM1 = 1? (TT0CTL2) No Yes No Yes Count value matches CCR1 register value? No Yes 16-bit counter cleared and started. INTTT0CC0 signal generated. 16-bit counter cleared and started.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (2) Encoder compare mode operation timing (a) Basic timing 1 [Register setting conditions] • TT0CTL2.TT0ECM1 and TT0CTL2.TT0ECM0 bits = 01 The 16-bit counter is cleared to 0000H when its count value matches the value of the CCR0 buffer register. • TT0CTL2.TT0LDE bit = 1 The set value of the TT0CCR0 register is transferred to the 16-bit counter when it overflows. • TT0IOC3.TT0SCE bit = 0, and TT0IOC3.TT0ECS1 and TT0IOC3.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) When the 16-bit counter starts operating (TT0CE bit = 0 → 1), the set value of the TT0TCW register is transferred to the counter and the 16-bit counter starts operating. When the count value of the counter matches the value of the CCR0 buffer register, the compare match interrupt request signal (INTTT0CC0) is generated. Because the TT0ECM0 bit = 1, the 16-bit counter is cleared to 0000H if the next count operation is counting up.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (b) Basic timing 2 [Register setting condition] • TT0CTL2.TT0ECM1 and TT0CTL2.TT0ECM0 bits = 00 The 16-bit counter is not cleared even when its count value matches the value of the CCRn buffer register (a = 0, 1). • TT0CTL2.TT0LDE bit = 0 The set value of the TT0CCR0 register is not transferred to the 16-bit counter after the counter underflows. • TT0IOC3.TT0SCE bit = 0, and TT0IOC3.TT0ECS1 and TT0IOC3.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) When the 16-bit counter starts operating (TT0CE bit = 0 → 1), the set value of the TT0TCW register is transferred to the 16-bit counter and the counter starts operating. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTT0CC0) is generated.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) (c) Basic timing 3 [Register setting condition] • TT0CTL2.TT0ECM1 and TT0CTL2.TT0ECM0 bits = 11 The count value of the 16-bit counter is cleared to 0000H when its value matches the value of the CCR0 buffer register. The count value of the 16-bit counter is cleared to 0000H when its value matches the value of the CCR1 buffer register. • Setting of the TT0CTL2.TT0LDE bit is invalid. • TT0IOC3.TT0SCE bit = 0, and TT0IOC3.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) When the 16-bit counter starts operating (TT0CE bit = 0 → 1), the set value of the TT0TCW register is transferred to the 16-bit counter and the counter starts operating. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTT0CC0) is generated. At this time, the 16-bit counter is cleared to 0000H if the next count operation is counting up.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 10 16-BIT INTERVAL TIMER M (TMM) CHAPTER 10 16-BIT INTERVAL TIMER M (TMM) The V850ES/JG3-H and V850ES/JH3-H have four TMM channels (TMMn). 10.1 Overview TMMn has the following features. • Interval function • 8 clocks selectable • 16-bit counter × 1 (The 16-bit counter cannot be read during timer count operation.) • Compare register × 1 (The compare register cannot be written during timer counter operation.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 10 16-BIT INTERVAL TIMER M (TMM) 10.2 Configuration TMMn includes the following hardware. Table 10-1. Configuration of TMMn Item Configuration Timer register 16-bit counter Register TMMn compare register 0 (TMnCMP0) Control register TMMn control register 0 (TMnCTL0) Figure 10-1.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 10 16-BIT INTERVAL TIMER M (TMM) (1) 16-bit counter This is a 16-bit counter that counts the internal clock. The 16-bit counter cannot be read or written. (2) TMMn compare register 0 (TMnCMP0) The TMnCMP0 register is a 16-bit compare register. This register can be read or written in 16-bit units. Reset sets this register to 0000H. Software can be used to always write the same value to the TMnCMP0 register. Rewriting the TMnCMP0 register is prohibited when the TMnCTL0.
PAGE 569
V850ES/JG3-H, V850ES/JH3-H CHAPTER 10 16-BIT INTERVAL TIMER M (TMM) 10.3 Registers (1) TMMn control register (TMnCTL0) The TMnCTL0 register is an 8-bit register that controls the TMMn operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. Software can be used to always write the same value to the TMnCTL0 register. Remark n = 0 to 3 R01UH0042EJ0500 Rev.5.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 10 16-BIT INTERVAL TIMER M (TMM) After reset: 00H R/W Address: TM0CTL0 FFFFFA80H, TM1CTL0 FFFFFA90H, TM2CTL0 FFFFFAA0H, TM3CTL0 FFFFFAB0H 6 <7> TMnCTL0 TMnCE 5 0 4 0 3 0 2 0 1 0 TMnCKS2 TMnCKS1 TMnCKS0 (n = 0 to 3) TMnCE Internal clock operation enable/disable specification 0 TMMn operation disabled (16-bit counter reset asynchronously). Operation clock application stopped. 1 TMMn operation enabled. Operation clock application started.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 10 16-BIT INTERVAL TIMER M (TMM) 10.4 Operation Caution Do not set the TMnCMP0 register to FFFFH. 10.4.1 Interval timer mode In the interval timer mode, an interrupt request signal (INTTMnEQ0) is generated at the specified interval if the TMnCTL0.TMnCE bit is set to 1. Figure 10-2. Configuration of Interval Timer Clear Count clock selection INTTMnEQ0 signal 16-bit counter Match signal TMnCE bit Remark TMnCMP0 register n = 0 to 3 Figure 10-3.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 10 16-BIT INTERVAL TIMER M (TMM) When the TMnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts counting. When the count value of the 16-bit counter matches the value of the TMnCMP0 register, the 16-bit counter is cleared to 0000H and a compare match interrupt request signal (INTTMnEQ0) is generated. The interval can be calculated by the following expression.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 10 16-BIT INTERVAL TIMER M (TMM) (1) Interval timer mode operation flow Figure 10-5. Software Processing Flow in Interval Timer Mode FFFFH D 16-bit counter D D 0000H TMnCE bit TMnCMP0 register D INTTMnEQ0 signal <1> <2> <1> Count operation start flow START Register initial setting TMnCTL0 register (TMnCKS0 to TMnCKS2 bits) TMnCMP0 register TMnCE bit = 1 The initial setting of these registers is performed before setting the TMnCE bit to 1.
PAGE 574
V850ES/JG3-H, V850ES/JH3-H CHAPTER 10 16-BIT INTERVAL TIMER M (TMM) (2) Interval timer mode operation timing Caution Do not set the TMnCMP0 register to FFFFH. (a) Operation if TMnCMP0 register is set to 0000H If the TMnCMP0 register is set to 0000H, the INTTMnEQ0 signal is generated at each count clock. The value of the 16-bit counter is always 0000H.
PAGE 575
V850ES/JG3-H, V850ES/JH3-H CHAPTER 10 16-BIT INTERVAL TIMER M (TMM) 10.4.2 Cautions (1) It takes the 16-bit counter up to the following time to start counting after the TMnCTL0.TMnCE bit is set to 1, depending on the count clock selected.
PAGE 576
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION CHAPTER 11 MOTOR CONTROL FUNCTION 11.1 Functional Overview Timer AB1 (TAB1) and the TMQ0 option (TMQOP0) can be used as an inverter function that controls a motor. It performs a tuning operation with timer AA4 (TAA4) and A/D conversion of the A/D converter can be started when the value of TAB1 matches the value of TAA4. The following operations can be performed as motor control functions.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION 11.2 Configuration The motor control function consists of the following hardware.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION Figure 11-1.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION Figure 11-2.
PAGE 580
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION (1) TAB1 dead-time compare register (TAB1DTC) The TAB1DTC register is a 10-bit compare register that specifies the dead-time value. Rewriting this register is prohibited when the TAB1CTL0.TAB1CE bit = 1. This register can be read or written in 16-bit units. Reset sets this register to 0000H. Caution When generating a dead-time period, set the TAB1DTC register to 1 or higher. Note, when the operation is stopped (TAB1CTL0.
PAGE 581
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION 11.3 Control Registers (1) TAB1 option register 1 (TAB1OPT1) The TAB1OPT1 register is an 8-bit register that controls the interrupt request signal generated by the timer Q option function. This register can be rewritten when the TAB1CTL0.TAB1CE bit is 1. Two rewrite modes (batch write mode and anytime write mode) can be selected, depending on the setting of the TAB1OPT0.TAB1CMS bit. This register can be read or written in 8-bit or 1-bit units.
PAGE 582
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION (2) TAB1 option register 2 (TAB1OPT2) The TAB1OPT2 register is an 8-bit register that controls the timer Q option function. This register can be rewritten when the TAB1CTL0.TAB1CE bit is 1. However, rewriting the TAB1DTM bit is prohibited when the TAB1CE bit is 1. The same value can be rewritten. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
PAGE 583
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION (2/2) TAB1ATM3 TAB1ATM3 mode selection 0 Output A/D trigger signal (TABTADT0) for INTTAA4CC1 interrupt while dead-time counter is counting up. 1 Output A/D trigger signal (TABTADT0) for INTTAA4CC1 interrupt while dead-time counter is counting down. TAB1ATM2 TAB1ATM2 mode selection 0 Output A/D trigger signal (TABTADT0) for INTTAA4CC0 interrupt while dead-time counter is counting up.
PAGE 584
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION (3) TAB1 I/O control register 3 (TAB1IOC3) The TAB1IOC3 register is an 8-bit register that controls the output of the timer Q option function. To output from the TOAB1Tm pin, set the TAB1IOC0.TAB1OEm bit to 1 and then set the TAB1IOC3 register. The TAB1IOC3 register can be rewritten only when the TAB1CTL0.TAB1CE bit is 0. Rewriting each bit of the TAB1IOC3 register is prohibited when the TAB1CTL0.
PAGE 585
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION (a) Output from TOAB1Tm and TOAB1Bm pins The TOAB1Tm pin output is controlled by the TAB1IOC0.TAB1OLm and TAB1IOC0.TAB1OEm bits. The TOAB1Bm pin output is controlled by the TAB1IOC3.TAB1OLBm and TAB1IOC3.TAB1OEBm bits. The timer output with each setting in the 6-phase PWM output mode is shown below. Figure 11-3.
PAGE 586
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION Table 11-1. TOAB1Tm Pin Output TAB1OLm Bit TAB1OEm Bit TAB1CE Bit 0 0 x Low-level output 1 0 Low-level output 1 TOAB1Tm positive-phase output 0 x High-level output 1 0 High-level output 1 TOAB1Tm negative-phase output 1 Remark TOAB1Tm Pin Output m = 1 to 3 Table 11-2.
PAGE 587
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION (1/2) After reset: 00H R/W <7> HZA0CTLn Address: HZA0CTL0 FFFFF590H, HZA0CTL1 FFFFF591H <6> 5 4 <3> <2> HZA0DCEn HZA0DCMn HZA0DCNn HZA0DCPn HZA0DCTn HZA0DCCn 1 <0> 0 HZA0DCFn (n = 0, 1) High-impedance output control HZA0DCEn 0 Disable high-impedance output control operation. Pins can function as output pins. 1 Enable high-impedance output control operation.
PAGE 588
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION (2/2) High-impedance output trigger bit HZA0DCTn 0 No operation 1 Pins are made to go into a high-impedance state by software and the HZA0DCFn bit is set to 1. • If an edge indicating abnormality is input to the external pin (which is detected according to the setting of the HZA0DCNn and HZA0DCPn bits), the HZA0DCTn bit is invalid even if it is set to 1. • The HZA0DCTn bit is always 0 when it is read because it is a software-triggered bit.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION Figure 11-4. High-Impedance Output Controller Configuration TOAA1OFF/ INTP09 Analog filter TOAB1OFF/ INTP16 Analog filter Edge detection INTP16 Edge detection INTP09 HZA0CTL1 X2 Main oscillator TOAA11 TMQOP TOAB1B1 HZA0CTL0 PLL X1 TAA1 Clock monitor circuit TOAB1T1 TOAB1B2 TOAB1T2 TOAB1B3 TOAB1T3 Remark Also see Figures 11-1 and 11-2. R01UH0042EJ0500 Rev.5.
PAGE 590
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION (a) Setting procedure (i) Setting of high-impedance control operation <1> Set the HZA0DCMn, HZA0DCNn, and HZA0DCPn bits. <2> Set the HZA0DCEn bit to 1 (enable high-impedance control). (ii) Changing setting after enabling high-impedance control operation <1> Clear the HZA0DCEn bit to 0 (to stop the high-impedance control operation). <2> Change the setting of the HZA0DCMn, HZA0DCNn, and HZA0DCPn bits.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION 11.4 Operation 11.4.1 System outline (1) Outline of 6-phase PWM output The 6-phase PWM output mode is used to generate a 6-phase PWM output wave, by using the timer AB1 (TAB1) and the TMQ option (TMQOPA) in combination. The 6-phase PWM output mode is enabled by setting the TAB1CTL1.TAB1MD2 to TAB1CTL1.TAB1MD0 bits of TAB1 to “111”. One 16-bit counter and four 16-bit compare registers of TAB1 are used to generate a basic 3-phase wave.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION Figure 11-5.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION Figure 11-6.
PAGE 594
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION (2) Interrupt requests Two types of interrupt requests are available: the INTTAB1CC0 (crest interrupt) signal and INTTAB1OV (valley interrupt) signal. The INTTAB1CC0 and INTTAB1OV signals can be culled by using the TAB1OPT1 register. For details of culling interrupts, see 11.4.3 Interrupt culling function.
PAGE 595
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION Figure 11-7.
PAGE 596
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION 11.4.2 Dead-time control (generation of negative-phase wave signal) (1) Dead-time control mechanism In the 6-phase PWM output mode, compare registers 1 to 3 (TAB1CCR1, TAB1CCR2, and TAB1CCR3) are used to set the duty factor, and compare register 0 (TAB1CCR0) is used to set the cycle.
PAGE 597
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION (2) PWM output of 0%/100% The V850ES/V850ES/JG3-H and V850ES/JH3-H are capable of 0% wave output and 100% wave output for PWM output. A low level is continuously output from the TOAB1Tm pin as the 0% wave output. A high level is continuously output from the TOAB1Tm pin as the 100% wave output. A 0% wave is output by setting the TAB1CCRm register to “M + 1” when the TAB1CCR0 register = M.
PAGE 598
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION Figure 11-10. 100% PWM Output Waveform (With Dead Time) 16-bit counter i i i TAB1CCR0 register i i M TAB1CCR1 register CCR1 buffer register i 0000H i 0000H i 0000H <1> TOAB1T1 pin output TOAB1B1 pin output Forced timing of timer output 0000H i 0000H i <2> 100% output i <3> i <4> 100% output <1> 100% output is selected by the valley interrupt (with a match with the 16-bit counter).
PAGE 599
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION Figure 11-11.
PAGE 600
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION Figure 11-12.
PAGE 601
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION (4) Automatic dead-time width narrowing function (TAB1OPT2.TAB1DTM bit = 1) The dead-time width can be automatically narrowed in the vicinity of 0% output or 100% output by setting the TAB1OPT2.TAB1DTM bit to 1. By setting the TAB1DTM bit to 1, the dead-time counter is not cleared, but starts down counting if the TOAB1m (internal signal) output of timer AB changes during dead-time counting.
PAGE 602
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION (5) Dead-time control in case of incorrect setting Usually, the TOAB1m (internal signal) output of TAB1 changes only once during dead-time counting, only in the vicinity of 0% and 100% output. This section shows an example where the TAB1CCR0 register (carrier cycle) and TAB1DTC register (dead-time value) are incorrectly set.
PAGE 603
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION 11.4.3 Interrupt culling function • The interrupts to be culled are INTTAB1CC0 (crest interrupt) and INTTAB1OV (valley interrupt). • The TAB1OPT1.TAB1ICE bit is used to enable output of the INTTAB1CC0 interrupt and the number of times the interrupt is to be culled. • The TAB1OPT1.TAB1IOE bit is used to enable output of the INTTAB1OV interrupt and the number of times the interrupt is to be culled. • The TAB1OPT1.TAB1ID4 to TAB1OPT1.
PAGE 604
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION (1) Interrupt culling operation Figure 11-15. Interrupt Culling Operation When TAB1OPT1.TAB1ICE Bit = 1, TAB1OPT1.TAB1IOE Bit = 1, TAB1OPT2.TAB1RDE Bit = 1 (Crest/Valley Interrupt Output) 16-bit counter TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00000 (not culled) INTTAB1CC0 signal INTTAB1OV signal TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00001 (1 mask) INTTAB1CC0 signal INTTAB1OV signal TAB1OPT1.TAB1ID4 to TAB1OPT1.
PAGE 605
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION Figure 11-16. Interrupt Culling Operation When TAB1OPT1.TAB1ICE Bit = 1, TAB1OPT1.TAB1IOE Bit = 0, TAB1OPT2.TAB1RDE Bit = 1 (Crest Interrupt Output) 16-bit counter TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00000 (not culled) INTTAB1CC0 signal INTTAB1OV signal TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00001 (1 mask) INTTAB1CC0 signal INTTAB1OV signal TAB1OPT1.TAB1ID4 to TAB1OPT1.
PAGE 606
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION Figure 11-17. Interrupt Culling Operation When TAB1OPT1.TAB1ICE Bit = 0, TAB1OPT1.TAB1IOE Bit = 1, TAB1OPT2.TAB1RDE Bit = 1 (Valley Interrupt Output) 16-bit counter TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00000 (not culled) INTTAB1CC0 signal INTTAB1OV signal TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00001 (1 mask) INTTAB1CC0 signal INTTAB1OV signal TAB1OPT1.TAB1ID4 to TAB1OPT1.
PAGE 607
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION (2) To alternately output crest interrupt (INTTAB1CC0) and valley interrupt (INTTAB1OV) To alternately output the crest and valley interrupts, set both the TAB1OPT1.TAB1ICE and TAB1OPT1.TAB1IOE bits to 1. Figure 11-18. Crest/Valley Interrupt Output (a) TAB1OPT0.TAB1CMS bit = 0, TAB1OPT2.
PAGE 608
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION (3) To output only crest interrupt (INTTAB1CC0) Set the TAB1OPT1.TAB1ICE bit to 1 and clear the TAB1OPT1.TAB1IOE bit to 0. Figure 11-19. Crest Interrupt Output (a) TAB1OPT0.TAB1CMS bit = 0, TAB1OPT2.
PAGE 609
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION (4) To output only valley interrupt (INTTAB1OV) Clear the TAB1OPT1.TAB1ICE bit to 0 and set the TAB1IOE bit to 1. Figure 11-20. Valley Interrupt Output (a) TAB1OPT0.TAB1CMS bit = 0, TAB1OPT2.
PAGE 610
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION 11.4.4 Operation to rewrite register with transfer function The following seven registers are provided with a transfer function and are used to control a motor. Each of the registers has a buffer register.
PAGE 611
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION (1) Anytime rewrite mode This mode is set by setting the TAB1OPT0.TAB1CMS bit to 1. The setting of the TAB1OPT2.TAB1RDE bit is ignored. In this mode, the value written to each register with a transfer function is immediately transferred to an internal buffer register and compared with the value of the counter.
PAGE 612
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION (b) Rewriting TAB1CCRm register Figure 11-24 shows the timing of rewriting before the value of the 16-bit counter matches the value of the TAB1CCRm register (<1> in Figure 11-23), and Figure 11-25 shows the timing of rewriting after the value of the 16-bit counter matches the value of the TAB1CCRm register (<2> in Figure 11-23). Figure 11-23.
PAGE 613
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION Figure 11-24. Example of Rewriting TAB1CCR1 to TAB1CCR3 Registers (Rewriting Before Match Occurs) (a) If the TAB1CCRm register is rewritten before its value matches the value of the 16-bit counter, the register value will match the value of the 16-bit counter after the register has been rewritten. Consequently, the new register value is immediately reflected.
PAGE 614
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION Figure 11-25.
PAGE 615
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION (2) Batch rewrite mode (transfer mode) This mode is set by clearing the TAB1OPT0.TAB1CMS bit to 0, the TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits to 00000, and the TAB1OPT2.TAB1RDE bit to 0. In this mode, the values written to each compare register are transferred to the internal buffer register all at once at the transfer timing and compared with the counter value.
PAGE 616
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION Figure 11-26.
PAGE 617
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION (b) Rewriting TAB1CCR0 register When rewriting the TAB1CCR0 register in the batch rewrite mode, the output waveform differs depending on whether transfer occurs at the crest (match between the 16-bit counter value and TAB1CCR0 register value) or at the valley (match between the 16-bit counter value and 0001H).
PAGE 618
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION The transfer timing in Figure 11-28 is at the point where the crest timing occurs. While the 16-bit counter is counting down, the cycle changes and an asymmetrical triangular wave is output. Because the cycle changes, rewrite the duty factor (voltage data value). Figure 11-28.
PAGE 619
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION Figure 11-29.
PAGE 620
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION (c) Rewriting TAB1CCRm register Figure 11-30.
PAGE 621
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION (3) Intermittent batch rewrite mode (transfer culling mode) This mode is set by clearing the TAB1OPT0.TAB1CMS bit to 0 and setting the TAB1OPT2.TAB1RDE bit to 1. In this mode, the values written to each compare register are transferred to the internal buffer register all at once after the culled transfer timing and compared with the counter value.
PAGE 622
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION Figure 11-31.
PAGE 623
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION (b) Rewriting TAB1CCR0 register When rewriting the TAB1CCR0 register in the intermittent batch mode, the output waveform differs depending on where the occurrence of the crest or valley interrupt is specified by the interrupt culling setting. The following figure illustrates the change of the output waveform when interrupts are culled. Figure 11-32.
PAGE 624
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION Figure 11-33.
PAGE 625
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION (c) Rewriting TAB1CCR1 to TAB1CCR3 registers • Transfer at crest when crest interrupt is set Because the register is transferred at the transfer timing of the crest interrupt, an asymmetrical triangular wave is output. Figure 11-34. Rewriting TAB1CCR1 Register (TAB1OPT1.TAB1ICE Bit = 1, TAB1OPT1.TAB1IOE Bit = 0, TAB1OPT1.TAB1ID4 to TAB1OPT1.
PAGE 626
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION • Transfer at valley when valley interrupt is set Because the register is transferred at the transfer timing of the valley interrupt, a symmetrical triangular wave is output. Figure 11-35. Rewriting TAB1CCR1 Register (TAB1OPT1.TAB1ICE Bit = 1, TAB1OPT1.TAB1IOE Bit = 1, TAB1OPT1.TAB1ID4 to TAB1OPT1.
PAGE 627
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION (4) Rewriting TAB1OPT0.TAB1CMS bit The TAB1CMS bit can select the anytime rewrite mode and batch rewrite mode. This bit can be rewritten during timer operation (when TAB1CTL0.TAB1CE bit = 1). However, the operation and caution illustrated in Figure 11-36 are necessary. If the TAB1CCR1 register is written when the TAB1CMS bit is cleared to 0, a transfer request signal (internal signal) is set.
PAGE 628
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION 11.4.5 TAA4 tuning operation for A/D conversion start trigger signal output This section explains the tuning operation of TAA4 and TAB1 in the 6-phase PWM output mode. In the 6-phase PWM output mode, the tuning operation is performed with TAB1 serving as the master and TAA4 as a slave.
PAGE 629
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION (e) Set the TAA4CE bit to 1 and set the TAB1CE bit to 1 immediately after that to start the 6-phase PWM output operation Rewriting the TAB1CTL0, TAB1CTL1, TAB1IOC1, TAB1IOC2, TAA4CTL0, and TAA4CTL1 registers is prohibited during operation. The operation and the PWM output waveform are not guaranteed if any of these registers is rewritten during operation. However, rewriting the TAB1CTL0.TAB1CE bit to clear it is permitted.
PAGE 630
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION Figure 11-37.
PAGE 631
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION 11.4.6 A/D conversion start trigger output function The V850ES/JG3-H and V850ES/JH3-H have a function to select four trigger sources (INTTAB1OV, INTTAB1CC0, INTTAA4CC0, INTTAA4CC1) to generate the A/D conversion start trigger signal (TABTADT0). The trigger sources are specified by the TAB1OPT2.TAB1AT0 to TAB1OPT2.TAB1AT3 bits. • TAB1AT0 bit = 1: A/D conversion start trigger signal generated when INTTAB1OV (counter underflow) occurs.
PAGE 632
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION Cautions 1. The A/D conversion start trigger signal output that is set by the TAB1AT2 and TAB1AT3 bits can be used only when TAA4 is performing a tuning operation as the slave timer of TAB1. If TAB1 and TAA4 are not performing a tuning operation, or if a mode other than the 6-phase PWM output mode is used, the output cannot be guaranteed. 2. The TAB1 signal output is internally used to identify whether the 16-bit counter is counting up or down.
PAGE 633
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION Figure 11-38. Example of A/D Conversion Start Trigger (TABTADT0) Signal Output (TAB1OPT1.TAB1ICE Bit = 1, TAB1OPT1.TAB1IOE Bit = 1, TAB1OPT1.TAB1ID4 to TAB1OPT1.
PAGE 634
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION Figure 11-39. Example of A/D Conversion Start Trigger (TABTADT0) Signal Output (TAB1OPT1.TAB1ICE Bit = 0, TAB1OPT1.TAB1IOE Bit = 1, TAB1OPT1.TAB1ID4 to TAB1OPT1.
PAGE 635
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION (1) Operation under boundary condition (operation when 16-bit counter matches INTTAA4CC0 signal) Table 11-3.
PAGE 636
V850ES/JG3-H, V850ES/JH3-H CHAPTER 12 REAL-TIME COUNTER CHAPTER 12 REAL-TIME COUNTER 12.1 Functions The real-time counter (RTC) has the following features. • Counting up to 99 years using year, month, day-of-week, day, hour, minute, and second sub-counters provided • Year, month, day-of-week, day, hour, minute, and second counter display using BCD codesNote 1 • Alarm interrupt function • Constant-period interrupt function (period: 1 month to 0.5 second) • Interval interrupt function (period: 1.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 12 REAL-TIME COUNTER 12.2 Configuration The real-time counter includes the following hardware. Table 12-1.
PAGE 638
V850ES/JG3-H, V850ES/JH3-H CHAPTER 12 REAL-TIME COUNTER Figure 12-1. Block Diagram of Real-Time Counter CLOE1 RTC1HZ Hour alarm Minute alarm Day-of-week alarm Selector INTRTC1 Count clock = 32.
PAGE 639
V850ES/JG3-H, V850ES/JH3-H CHAPTER 12 REAL-TIME COUNTER 12.2.1 Pin configuration The RTC outputs included in the real-time counter are alternatively used as shown in Table 12-2. The port function must be set when using each pin (see Table 4-20 Using Port Pin as Alternate-Function Pin). Table 12-2.
PAGE 640
V850ES/JG3-H, V850ES/JH3-H CHAPTER 12 REAL-TIME COUNTER 12.3 Registers The real-time counter is controlled by the following 18 registers. (1) Real-time counter control register 0 (RC1CC0) The RC1CC0 register selects the real-time counter input clock. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
PAGE 641
V850ES/JG3-H, V850ES/JH3-H After reset: 00H 7 RC1CC1 RTCE CHAPTER 12 REAL-TIME COUNTER R/W 6 0 Address: FFFFFADEH 5 3 2 1 0 AMPM CT2 CT1 CT0 4 CLOE1 RCTE CLOE0 Control of operation of each counter 0 Stops counter operation. 1 Enables counter operation. CLOE1 RTC1HZ pin output control 0 Disables RTC1HZ pin output (1 Hz) 1 Enables RTC1HZ pin output (1 Hz) CLOE0 RTCCL pin output control 0 Disables RTCCL pin output (32.768 kHz) 1 Enables RTCCL pin output (32.
PAGE 642
V850ES/JG3-H, V850ES/JH3-H CHAPTER 12 REAL-TIME COUNTER (3) Real-time counter control register 2 (RC1CC2) The RC1CC2 register is an 8-bit register that controls the alarm interrupt function and waiting of counters. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
PAGE 643
V850ES/JG3-H, V850ES/JH3-H CHAPTER 12 REAL-TIME COUNTER (4) Real-time counter control register 3 (RC1CC3) The RC1CC3 register is an 8-bit register that controls the interval interrupt function and RTCDIV pin. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H 7 RC1CC3 RINTE R/W 6 CLOE2 Address: FFFFFAE0H 5 4 CKDIV RINTE 0 3 2 1 0 0 ICT2 ICT1 ICT0 Interval interrupt (INTRTC2) control 0 Does not generate interval interrupt.
PAGE 644
V850ES/JG3-H, V850ES/JH3-H CHAPTER 12 REAL-TIME COUNTER (5) Sub-count register (RC1SUBC) The RC1SUBC register is a 16-bit register that counts the reference time of 1 second of the real-time counter. It takes a value of 0000H to 7FFFH and counts one second with a clock of 32.768 kHz. This register is read-only, in 16-bit units. Reset sets this register to 0000H. Cautions 1 When a correction is made by using the RC1SUBU register, the value may become 8000H or more. 2.
PAGE 645
V850ES/JG3-H, V850ES/JH3-H CHAPTER 12 REAL-TIME COUNTER (7) Minute count register (RC1MIN) The RC1MIN register is an 8-bit register that takes a value of 0 to 59 (decimal) and indicates the count value of minutes. It counts up when the second counter overflows. When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 kHz) later. Set a decimal value of 00 to 59 to this register in BCD code. This register can be read or written 8-bit units.
PAGE 646
V850ES/JG3-H, V850ES/JH3-H CHAPTER 12 REAL-TIME COUNTER Table 12-3 shows the relationship among the AMPM bit setting value, RC1HOUR register value, and time. Table 12-3. Time Digit Display 12-Hour Display (AMPM Bit = 0) 24-Hour Display (AMPM Bit = 1) Time Time RC1HOUR Register Value RC1HOUR Register Value 0:00 a.m. 12 H 0:00 00H 1:00 a.m. 01 H 1:00 01 H 2:00 a.m. 02 H 2:00 02 H 3:00 a.m. 03 H 3:00 03 H 4:00 a.m. 04 H 4:00 04 H 5:00 a.m. 05 H 5:00 05 H 6:00 a.m.
PAGE 647
V850ES/JG3-H, V850ES/JH3-H CHAPTER 12 REAL-TIME COUNTER (9) Day count register (RC1DAY) The RC1DAY register is an 8-bit register that takes a value of 1 to 31 (decimal) and indicates the count value of days. It counts up when the hour counter overflows. This counter counts as follows.
PAGE 648
V850ES/JG3-H, V850ES/JH3-H CHAPTER 12 REAL-TIME COUNTER (10) Day-of-week count register (RC1WEEK) The RC1WEEK register is an 8-bit register that takes a value of 0 to 6 (decimal) and indicates the day-of-week count value. It counts up in synchronization with the day counter. When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (2 x 32.768 kHz) later. Set a decimal value of 00 to 06 to this register in BCD code.
PAGE 649
V850ES/JG3-H, V850ES/JH3-H CHAPTER 12 REAL-TIME COUNTER (11) Month count register (RC1MONTH) The RC1MONTH register is an 8-bit register that takes a value of 1 to 12 (decimal) and indicates the count value of months. It counts up when the day counter overflows. When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (2 x 32.768 kHz) later. Set a decimal value of 01 to 12 to this register in BCD code. This register can be read or written in 8-bit units.
PAGE 650
V850ES/JG3-H, V850ES/JH3-H CHAPTER 12 REAL-TIME COUNTER (13) Watch error correction register (RC1SUBU) The RC1SUBU register (8-bit) can be used to correct the watch with high accuracy when the watch is early or late, by changing the value (reference value: 7FFFH) overflowing from the sub-count register (RSUBC) to the second counter register. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. Remarks 1.
PAGE 651
V850ES/JG3-H, V850ES/JH3-H CHAPTER 12 REAL-TIME COUNTER (14) Alarm minute setting register (RC1ALM) The RC1ALM register (8-bit) is used to set minutes of alarm. This register can be read or written in 8-bit units. Reset sets this register to 00H. Caution Set a decimal value of 00 to 59 to this register in BCD code. If a value outside the range is set, the alarm is not detected.
PAGE 652
V850ES/JG3-H, V850ES/JH3-H CHAPTER 12 REAL-TIME COUNTER (16) Alarm day-of-week setting register (RC1ALW) The RC1ALW register is used to set the day-of-week of the alarm. This register can be read or written in 8-bit units. Reset sets this register to 00H. Caution See 12.4.5 Changing INTRTC1 interrupt setting during the real-time counter operation when rewriting the RC1ALW register while the real-time counter operates (RC1PWR bit = 1).
PAGE 653
V850ES/JG3-H, V850ES/JH3-H CHAPTER 12 REAL-TIME COUNTER (a) Alarm interrupt setting examples (RC1ALM, RC1ALH, and RC1ALW setting examples) Tables 12-4 and 12-5 show setting examples if Sunday is RC1WEEK = 00, Monday is RC1WEEK = 01, Tuesday is RC1WEEK = 02, ···, and Saturday is RC1WEEK = 06. Table 12-4. Alarm Setting Example if AMPM = 0 (RC1HOUR Register 12-Hour Display) Register RC1ALW RC1ALH RC1ALM 01H 07H 00H Alarm Setting Time Sunday, 7:00 a.m. Sunday/Monday, 00:15 p.m.
PAGE 654
V850ES/JG3-H, V850ES/JH3-H CHAPTER 12 REAL-TIME COUNTER (18) Prescaler compare register 0 (PRSCM0) The PRSCM0 register is an 8-bit compare register. This register can be read or written in 8-bit units. Reset sets this register to 00H. After reset: 00H PRSCM0 R/W Address: FFFFF8B1H PRSCM07 PRSCM06 PRSCM05 PRSCM04 PRSCM03 PRSCM02 PRSCM01 PRSCM00 Cautions 1. Do not rewrite the PRSCM0 register during real time counter operation. 2. Set the PRSCM0 register before setting the PRSM0.BGCE0 bit to 1. 3.
PAGE 655
V850ES/JG3-H, V850ES/JH3-H CHAPTER 12 REAL-TIME COUNTER 12.4 Operation 12.4.1 Initial settings The initial settings are set when operating the watch function and performing a fixed-cycle interrupt operation. Figure 12-2. Initial Setting Procedure Start RC1CC0.RC1PWR bit = 0 Setting RC1CKS RC1CC0.RC1PWR bit = 1 Setting AMPM and CT2 to CT0 Setting RC1SUBU Selects real-time counter (RTC) operation clock. Enables real-time counter (RTC) internal clock operation.
PAGE 656
V850ES/JG3-H, V850ES/JH3-H CHAPTER 12 REAL-TIME COUNTER 12.4.2 Rewriting each counter during the real-time counter operation Set as follows when rewriting each counter (RC1SEC, RC1MIN, RC1HOUR, RC1WEEK, RC1DAY, RC1MONTH, RC1YEAR) during the real-time counter operation (RC1PWR = 1, RTCE = 1). Figure 12-3. Rewriting Each Counter During The real-time counter Operation Start No RWST = 0? Checks whether previous writing to RC1SEC to RC1YEAR counters is completed.
PAGE 657
V850ES/JG3-H, V850ES/JH3-H CHAPTER 12 REAL-TIME COUNTER 12.4.3 Reading each counter during the real-time counter operation Set as follows when reading each counter (RC1SEC, RC1MIN, RC1HOUR, RC1WEEK, RC1DAY, RC1MONTH, RC1YEAR) during real-time counter operation (RC1PWR = 1). Figure 12-4. Reading Each Counter During The real-time counter Operation Start No RC1CC2.RWST bit = 0? Checks whether previous writing to RC1SEC to RC1YEAR is completed. Yes No RC1CC2.
PAGE 658
V850ES/JG3-H, V850ES/JH3-H CHAPTER 12 REAL-TIME COUNTER 12.4.4 Changing INTRTC0 interrupt setting during the real-time counter operation If the setting of the INTRTC0 interrupt (fixed-cycle interrupt) signal is changed while the real-time counter clock operates (PC1PWR = 1), the INTRCT0 interrupt waveform may include whiskers and unintended signals may be output.
PAGE 659
V850ES/JG3-H, V850ES/JH3-H CHAPTER 12 REAL-TIME COUNTER 12.4.5 Changing INTRTC1 interrupt setting during the real-time counter operation If the setting of the INTRTC1 interrupt (alarm interrupt) signal is changed while the real-time counter clock operates (RC1PWR = 1), the INTRCT1 interrupt waveform may include whiskers and unintended signals may be output.
PAGE 660
V850ES/JG3-H, V850ES/JH3-H CHAPTER 12 REAL-TIME COUNTER 12.4.6 Initial INTRTC2 interrupt settings Set as follows to set the INTRTC1 interrupt (interval interrupt). Figure 12-7. INTRTC2 Interrupt Setting Start RC1CC0.RC1PWR = 1 Setting RC1CC3.ICT2 to RC1CC3.ICT0 RC1CC3.RINTE = 1 Enables counter operation. <1> Selects INTRTC2 (interval) interrupt interval. <2> Enables INTRTC2 (interval) interrupt. End Caution Set <1> and <2> simultaneously or set <1> first.
PAGE 661
V850ES/JG3-H, V850ES/JH3-H CHAPTER 12 REAL-TIME COUNTER 12.4.7 Changing INTRTC2 interrupt setting during the real-time counter operation If the setting of the INTRTC2 interrupt (interval interrupt) is changed while the real-time counter clock operates (PC1PWR = 1), the INTRCT2 interrupt waveform may include whiskers and unintended signals may be output.
PAGE 662
V850ES/JG3-H, V850ES/JH3-H CHAPTER 12 REAL-TIME COUNTER 12.4.8 Initializing real-time counter The procedure for initializing the real-time counter is shown below. Figure 12-9. Initializing Real-Time Counter Start Setting RTCnMK bit Masks interrupt signal (INTRTCn) RC1CC3.CLOE2 bit = 0 RTCDIV interrupt disable processing RC1CC1.CLOE1 bit = 0 RC1CC1.CLOE0 bit = 0 RTC1HZ interrupt disable processing RTCCL interrupt disable processing RC1CC0.RC1PWR bit = 0 Initializes real-time counter (RTC).
PAGE 663
V850ES/JG3-H, V850ES/JH3-H CHAPTER 12 REAL-TIME COUNTER 12.4.9 Watch error correction example of real-time counter The watch error correction function corrects deviation in the oscillation frequency of a resonator connected to the V850ES/Jx3-H. Deviation, here, refers to steady-state deviation, which is deviation in the frequency when the resonator is designed. Next, the timing chart when an error has occurred in the input clock intended to be 32.768 kHz but a 32.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 12 REAL-TIME COUNTER As shown in Figure 12-10, the watch can be accurately counted by incrementing the RC1SUBC count value, if a positive error faster than 32.768 kHz occurs at the resonator. Similarly, if a negative error slower than 32.768 kHz occurs at the resonator, the watch can be accurately counted by decrementing the RC1SUBC count value. The RC1SUBC correction value is determined by using the RC1SUBU.F6 to RC1SUBU.F0 bits.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 12 REAL-TIME COUNTER (3) DEV bit The DEV bit determines when the setting by the F6 to F0 bits is enabled. The value set by the F6 to F0 bits is reflected upon the next timing, but not to the RC1SUBC count value every time. Table 12-6. DVE Bit Setting DEV Bit Value Timing of Reflecting Value to RC1SUBC 0 When RC1SEC is 00, 20, or 40 seconds. 1 When RC1SEC is 00 seconds.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 12 REAL-TIME COUNTER Table 12-7. Range of Frequencies That Can Be Corrected When DEV Bit = 0 F6 F5 to F0 RC1SUBC Correction Value Frequency of Connected Clock (Including Steady-State Deviation) 0 000000 No correction − 0 000001 No correction − 0 000010 Increments RC1SUBC count value by 2 once every 20 seconds 32.76810000 kHz 0 000011 Increments RC1SUBC count value by 4 once every 20 seconds 32.
PAGE 667
V850ES/JG3-H, V850ES/JH3-H CHAPTER 13 FUNCTIONS OF WATCHDOG TIMER 2 CHAPTER 13 FUNCTIONS OF WATCHDOG TIMER 2 13.1 Functions Watchdog timer 2 has the following functions.
PAGE 668
V850ES/JG3-H, V850ES/JH3-H CHAPTER 13 FUNCTIONS OF WATCHDOG TIMER 2 13.2 Configuration The following shows the block diagram of watchdog timer 2. Figure 13-1.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 13 FUNCTIONS OF WATCHDOG TIMER 2 13.3 Registers (1) Watchdog timer mode register 2 (WDTM2) The WDTM2 register sets the overflow time and operation clock of watchdog timer 2. This register can be read or written in 8-bit units. This register can be read any number of times, but it can be written only once following reset release. Reset sets this register to 67H. Caution Accessing the WDTM2 register is prohibited in the following statuses. For details, see 3.4.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 13 FUNCTIONS OF WATCHDOG TIMER 2 Table 13-2. Watchdog Timer 2 Clock Selection WDCS24 WDCS23 WDCS22 WDCS21 WDCS20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 Selected Clock 100 kHz (MIN.) 220 kHz (TYP.) 400 kHz (MAX.) 12 41.0 ms 18.6 ms 10.2 ms 13 81.9 ms 37.2 ms 20.5 ms 14 163.8 ms 74.5 ms 41.0 ms 15 327.7 ms 148.9 ms 81.9 ms 16 655.4 ms 297.9 ms 163.8 ms 17 1,310.7 ms 595.8 ms 327.
PAGE 671
V850ES/JG3-H, V850ES/JH3-H CHAPTER 13 FUNCTIONS OF WATCHDOG TIMER 2 (2) Watchdog timer enable register (WDTE) The counter of watchdog timer 2 is cleared and counting restarted by writing “ACH” to the WDTE register. The WDTE register can be read or written in 8-bit units. Reset sets this register to 9AH. After reset: 9AH R/W Address: FFFFF6D1H WDTE Cautions 1. When a value other than “ACH” is written to the WDTE register, an overflow signal is forcibly output. 2.
PAGE 672
V850ES/JG3-H, V850ES/JH3-H CHAPTER 14 REAL-TIME OUTPUT FUNCTION (RTO) CHAPTER 14 REAL-TIME OUTPUT FUNCTION (RTO) 14.1 Function The real-time output function transfers the data preset to the RTBL0 and RTBH0 registers to the output latches via hardware and outputs the data to an external device, at the same time as a timer interrupt occurs. The pins through which the data is output to an external device constitute a port called the real-time output (RTO) port.
PAGE 673
V850ES/JG3-H, V850ES/JH3-H CHAPTER 14 REAL-TIME OUTPUT FUNCTION (RTO) 14.2 Configuration The block diagram of RTO is shown below. Internal bus Figure 14-1.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 14 REAL-TIME OUTPUT FUNCTION (RTO) (1) Real-time output buffer registers 0L, 0H (RTBL0, RTBH0) The RTBL0 and RTBH0 registers are 4-bit registers that hold output data in advance. These registers are each mapped to independent addresses in the peripheral I/O register area. These registers can be read or written in 8-bit or 1-bit units. Reset sets these registers to 00H. If an operation mode of 4 bits × 1 channel or 2 bits × 1 channel is specified (RTPC0.
PAGE 675
V850ES/JG3-H, V850ES/JH3-H CHAPTER 14 REAL-TIME OUTPUT FUNCTION (RTO) 14.3 Registers RTO is controlled using the following two registers. • Real-time output port mode register 0 (RTPM0) • Real-time output port control register 0 (RTPC0) (1) Real-time output port mode register 0 (RTPM0) The RTPM0 register selects the real-time output port mode or port mode in 1-bit units. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
PAGE 676
V850ES/JG3-H, V850ES/JH3-H CHAPTER 14 REAL-TIME OUTPUT FUNCTION (RTO) (2) Real-time output port control register 0 (RTPC0) The RTPC0 register is a register that sets the operation mode and output trigger of the real-time output port. The relationship between the operation mode and output trigger of the real-time output port is as shown in Table 14-3. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 14 REAL-TIME OUTPUT FUNCTION (RTO) 14.4 Operation If the real-time output operation is enabled by setting the RTPC0.RTPOE0 bit to 1, the data of the RTBH0 and RTBL0 registers is transferred to the real-time output latch in synchronization with the generation of the selected transfer trigger (set by the RTPC0.EXTR0 and RTPC0.BYTE0 bits).
PAGE 678
V850ES/JG3-H, V850ES/JH3-H CHAPTER 14 REAL-TIME OUTPUT FUNCTION (RTO) 14.5 Usage (1) Disable real-time output. Clear the RTPC0.RTPOE0 bit to 0. (2) Perform initialization as follows. • Set the alternate-function pins of port 2 or port 5 After setting the PFC2.PFC2m bit and PFCE2.PFCE2m bit to the RTO pin, set the PMC2.PMC2m bit to 1 (m = 0 to 3). After setting the PFC5.PFC5m bit and PFCE5.PFCE5m bit to the RTO pin, set the PMC5.PMC5m bit to 1 (m = 0 to 5).
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 15 A/D CONVERTER CHAPTER 15 A/D CONVERTER 15.1 Overview The A/D converter converts analog input signals into digital values, has a resolution of 10 bits, and can handle 12 analog input signal channels (ANI0 to ANI11). The A/D converter has the following features. { 10-bit resolution { 12 channels { Successive approximation method { Operating voltage: AVREF0 = 3.0 to 3.6 V { Analog input voltage: 0 V to AVREF0 { The following functions are provided as operation modes.
PAGE 680
V850ES/JG3-H, V850ES/JH3-H CHAPTER 15 A/D CONVERTER 15.3 Configuration The block diagram of the A/D converter is shown below. Figure 15-1.
PAGE 681
V850ES/JG3-H, V850ES/JH3-H CHAPTER 15 A/D CONVERTER (1) Successive approximation register (SAR) The SAR compares the voltage value of the analog input signal with the output voltage of the compare voltage generation DAC (compare voltage), and holds the comparison result starting from the most significant bit (MSB). When the comparison result has been held down to the least significant bit (LSB) (i.e., when A/D conversion is complete), the contents of the SAR are transferred to the ADA0CRn register.
PAGE 682
V850ES/JG3-H, V850ES/JH3-H CHAPTER 15 A/D CONVERTER (12) Compare voltage generation DAC This compare voltage generation DAC is connected between AVREF0 and AVSS and generates a voltage for comparison with the analog input signal. (13) ANI0 to ANI11 pins These are analog input pins for the 12 A/D converter channels and are used to input analog signals to be converted into digital signals. Pins other than the one selected as the analog input by the ADA0S register can be used as input port pins.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 15 A/D CONVERTER 15.4 Registers The A/D converter is controlled by the following registers. • A/D converter mode registers 0, 1, 2 (ADA0M0, ADA0M1, ADA0M2) • A/D converter channel specification register 0 (ADA0S) • Power-fail compare mode register (ADA0PFM) The following registers are also used.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 15 A/D CONVERTER (2/2) Trigger mode specification ADA0TMD 0 Software trigger mode 1 External trigger mode/timer trigger mode A/D converter status display ADA0EF 0 A/D conversion stopped 1 A/D conversion in progress Cautions 1. Accessing the ADA0M0 register is prohibited in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 15 A/D CONVERTER (2) A/D converter mode register 1 (ADA0M1) The ADA0M1 register is an 8-bit register that specifies the conversion time. This register can be read or written in 8-bit or 1-bit units. Reset sets this bit to 00H.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 15 A/D CONVERTER Table 15-2. Conversion Time Selection in Normal Conversion Mode (ADA0HS1 Bit = 0) ADA0FR3 to ADA0FR0 Bits Stabilization Time 48 MHz 32 MHz 24 MHz + Conversion Time + Wait Time 0000 26/fXX + 52/fXX + 54/fXX Setting prohibited Setting prohibited 5.50 μs 0001 52/fXX + 104/fXX + 106/fXX 5.46 μs 8.19 μs Setting prohibited 0010 78/fXX + 156/fXX + 158/fXX 8.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 15 A/D CONVERTER Table 15-3. Conversion Time Selection in High-Speed Conversion Mode (ADA0HS1 Bit = 1) ADA0FR3 to ADA0FR0 Bits A/D Conversion Time Conversion Time 48 MHz 24 MHz 0000 52/fXX (+26/fXX) Setting prohibited Setting prohibited 2.17 μs 0001 104/fXX (+52/fXX) 2.17 μs 3.25 μs 4.33 μs 0010 156/fXX (+78/fXX) 3.25 μs 4.88 μs 6.50 μs 0011 208/fXX (+100/fXX) 4.33 μs 6.50 μs 8.67 μs 0100 260/fXX (+100/fXX) 5.42 μs 8.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 15 A/D CONVERTER (3) A/D converter mode register 2 (ADA0M2) The ADA0M2 register specifies the hardware trigger mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
PAGE 689
V850ES/JG3-H, V850ES/JH3-H CHAPTER 15 A/D CONVERTER (4) Analog input channel specification register 0 (ADA0S) The ADA0S register specifies the pin that inputs the analog voltage to be converted into a digital signal. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
PAGE 690
V850ES/JG3-H, V850ES/JH3-H CHAPTER 15 A/D CONVERTER (5) A/D conversion result registers n, nH (ADA0CRn, ADA0CRnH) The ADA0CRn and ADA0CRnH registers store the A/D conversion results. These registers are read-only, in 16-bit or 8-bit units. However, the ADA0CRn register is used for 16-bit access and the ADA0CRnH register for 8-bit access. The 10 bits of the conversion result are read to the higher 10 bits of the ADA0CRn register, and 0 is read to the lower 6 bits.
PAGE 691
V850ES/JG3-H, V850ES/JH3-H CHAPTER 15 A/D CONVERTER The relationship between the analog voltage input to the analog input pins (ANI0 to ANI11) and the A/D conversion result (ADA0CRn register) is as follows. SAR = INT ( VIN AVREF0 × 1,024 + 0.5) ADA0CRNote = SAR × 64 Or, (SAR − 0.5) × AVREF0 1,024 ≤ VIN < (SAR + 0.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 15 A/D CONVERTER (6) Power-fail compare mode register (ADA0PFM) The ADA0PFM register is an 8-bit register that sets the power-fail compare mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
PAGE 693
V850ES/JG3-H, V850ES/JH3-H CHAPTER 15 A/D CONVERTER (7) Power-fail compare threshold value register (ADA0PFT) The ADA0PFT register sets the compare value in the power-fail compare mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W 7 6 Address: FFFFF205H 5 4 3 2 1 0 ADA0PFT Caution In the following modes, write data to the ADA0PFT register while A/D conversion is stopped (ADA0M0.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 15 A/D CONVERTER 15.5 Operation 15.5.1 Basic operation <1> Set the operation mode, trigger mode, and conversion time for executing A/D conversion by using the ADA0M0, ADA0M1, ADA0M2, and ADA0S registers. When the ADA0CE bit of the ADA0M0 register is set, conversion is started in the software trigger mode and the A/D converter waits for a trigger in the external or timer trigger mode.
PAGE 695
V850ES/JG3-H, V850ES/JH3-H CHAPTER 15 A/D CONVERTER 15.5.2 Conversion operation timing Figure 15-3. Conversion Operation Timing (Continuous Conversion) (1) Operation in normal conversion mode (ADA0HS1 bit = 0) ADA0M0.ADA0CE bit First conversion Setup Processing state Sampling Second conversion A/D conversion Wait Conversion time Wait time Setup Sampling INTAD signal Stabilization time 2/fXX (MAX.) Sampling time 0.5/fXX (2) Operation in high-speed conversion mode (ADA0HS1 bit = 1) ADA0M0.
PAGE 696
V850ES/JG3-H, V850ES/JH3-H CHAPTER 15 A/D CONVERTER 15.5.3 Trigger mode The timing of starting the conversion operation is specified by setting the trigger mode. The trigger mode includes the software trigger mode and hardware trigger modes. The hardware trigger modes include timer trigger modes 0 and 1, and external trigger mode. The ADA0M0.ADA0TMD bit is used to set the trigger mode. The hardware trigger modes are set by the ADA0M2.ADA0TMD1 and ADA0M2.ADA0TMD0 bits.
PAGE 697
V850ES/JG3-H, V850ES/JH3-H CHAPTER 15 A/D CONVERTER (3) Timer trigger mode In this mode, converting the signal of the analog input pin (ANI0 to ANI11) specified by the ADA0S register is started by the compare match interrupt request signal (INTTAA2CC0 or INTTAA2CC1) of the capture/compare register connected to the timer. The INTTAA2CC0 or INTTAA2CC1 signal is selected by the ADA0TMD1 and ADA0TMD0 bits, and conversion is started at the rising edge of the specified compare match interrupt request signal.
PAGE 698
V850ES/JG3-H, V850ES/JH3-H CHAPTER 15 A/D CONVERTER 15.5.4 Operation mode Four operation modes are available as the modes in which to set the ANI0 to ANI11 pins: continuous select mode, continuous scan mode, one-shot select mode, and one-shot scan mode. The operation mode is selected by the ADA0M0.ADA0MD1 and ADA0M0.ADA0MD0 bits. (1) Continuous select mode In this mode, the voltage of one analog input pin selected by the ADA0S register is continuously converted into a digital value.
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 15 A/D CONVERTER Figure 15-5.
PAGE 700
V850ES/JG3-H, V850ES/JH3-H CHAPTER 15 A/D CONVERTER (3) One-shot select mode In this mode, the voltage of one analog input pin specified by the ADA0S register is converted into a digital value only once. The conversion result is stored in the ADA0CRn register corresponding to the analog input pin. In this mode, an analog input pin and an ADA0CRn register correspond on a one-to-one basis. When A/D conversion has been completed once, the INTAD signal is generated.
PAGE 701
V850ES/JG3-H, V850ES/JH3-H CHAPTER 15 A/D CONVERTER Figure 15-7.
PAGE 702
V850ES/JG3-H, V850ES/JH3-H CHAPTER 15 A/D CONVERTER 15.5.5 Power-fail compare mode The A/D conversion end interrupt request signal (INTAD) can be controlled as follows by the ADA0PFM and ADA0PFT registers. • When the ADA0PFM.ADA0PFE bit = 0, the INTAD signal is generated each time conversion is completed (normal use of the A/D converter). • When the ADA0PFE bit = 1 and when the ADA0PFM.
PAGE 703
V850ES/JG3-H, V850ES/JH3-H CHAPTER 15 A/D CONVERTER (1) Continuous select mode In this mode, the result of converting the voltage of the analog input pin specified by the ADA0S register is compared with the set value of the ADA0PFT register. If the result of power-fail comparison matches the condition set by the ADA0PFC bit, the conversion result is stored in the ADA0CRn register, and the INTAD signal is generated.
PAGE 704
V850ES/JG3-H, V850ES/JH3-H CHAPTER 15 A/D CONVERTER Figure 15-9.
PAGE 705
V850ES/JG3-H, V850ES/JH3-H CHAPTER 15 A/D CONVERTER (3) One-shot select mode In this mode, the result of converting the voltage of the analog input pin specified by the ADA0S register is compared with the set value of the ADA0PFT register. If the result of power-fail comparison matches the condition set by the ADA0PFC bit, the conversion result is stored in the ADA0CRn register, and the INTAD signal is generated.
PAGE 706
V850ES/JG3-H, V850ES/JH3-H CHAPTER 15 A/D CONVERTER Figure 15-11.
PAGE 707
V850ES/JG3-H, V850ES/JH3-H CHAPTER 15 A/D CONVERTER 15.6 Cautions (1) When A/D converter is not used When the A/D converter is not used, the power consumption can be reduced by clearing the ADA0M0.ADA0CE bit to 0. (2) Input range of ANI0 to ANI11 pins Input the voltage within the specified range to the ANI0 to ANI11 pins.
PAGE 708
V850ES/JG3-H, V850ES/JH3-H CHAPTER 15 A/D CONVERTER (5) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the contents of the ADA0S register are changed. If the analog input pin is changed during A/D conversion, therefore, the result of converting the previously selected analog input signal may be stored and the conversion end interrupt request flag may be set immediately before the ADA0S register is rewritten.
PAGE 709
V850ES/JG3-H, V850ES/JH3-H CHAPTER 15 A/D CONVERTER (7) AVREF0 pin (a) The AVREF0 pin is used as the power supply pin of the A/D converter and also supplies power to the alternatefunction ports. In an application where a backup power supply is used, be sure to supply the same potential as VDD to the AVREF0 pin as shown in Figure 15-15. (b) The AVREF0 pin is also used as the reference voltage pin of the A/D converter.
PAGE 710
V850ES/JG3-H, V850ES/JH3-H CHAPTER 15 A/D CONVERTER (10) Standby mode Because the A/D converter stops operating in the STOP mode, the conversion results are invalid, so power consumption can be reduced. Operations are resumed after the STOP mode is released, but the A/D conversion results after the STOP mode is released are invalid. When using the A/D converter after the STOP mode is released, clear the ADA0M0.
PAGE 711
V850ES/JG3-H, V850ES/JH3-H CHAPTER 15 A/D CONVERTER 15.7 How to Read A/D Converter Characteristics Table This section describes the terms related to the A/D converter. (1) Resolution The minimum analog input voltage that can be recognized, i.e., the ratio of an analog input voltage to 1 bit of digital output is called 1 LSB (least significant bit). The ratio of 1 LSB to the full scale is expressed as %FSR (full-scale range).
PAGE 712
V850ES/JG3-H, V850ES/JH3-H CHAPTER 15 A/D CONVERTER (3) Quantization error This is an error of ±1/2 LSB that inevitably occurs when an analog value is converted into a digital value. Because the A/D converter converts analog input voltages in a range of ±1/2 LSB into the same digital codes, a quantization error is unavoidable. This error is not included in the overall error, zero-scale error, full-scale error, integral linearity error, or differential linearity error in the characteristics table.
PAGE 713
V850ES/JG3-H, V850ES/JH3-H CHAPTER 15 A/D CONVERTER (5) Full-scale error This is the difference between the actually measured analog input voltage and its theoretical value when the digital output changes from 1…110 to 1…111 (full scale − 3/2 LSB). Figure 15-19. Full-Scale Error Digital output (lower 3 bits) Full-scale error 111 100 011 010 000 0 AVREF0 − 3 AVREF0 − 2 AVREF0 − 1 AVREF0 Analog input (LSB) (6) Differential linearity error Ideally, the width to output a specific code is 1 LSB.
PAGE 714
V850ES/JG3-H, V850ES/JH3-H CHAPTER 15 A/D CONVERTER (7) Integral linearity error This error indicates the extent to which the conversion characteristics differ from the ideal linear relationship. It indicates the maximum value of the difference between the actually measured value and its theoretical value where the zero-scale error and full-scale error are 0. Figure 15-21. Integral Linearity Error 1......1 Digital output Ideal line Integral linearity error 0......
PAGE 715
V850ES/JG3-H, V850ES/JH3-H CHAPTER 16 D/A CONVERTER CHAPTER 16 D/A CONVERTER 16.1 Functions The D/A converter has the following functions. 8-bit resolution × 2 channels (DA0CS0, DA0CS1) R-2R ladder method Settling time: 3 μs max. (when AVREF1 is 3.0 to 3.6 V and external load is 20 pF) Analog output voltage: AVREF1 × m/256 (m = 0 to 255; value set to DA0CSn register) Operation modes: Normal mode, real-time output mode Remark n = 0, 1 16.2 Configuration The D/A converter configuration is shown below.
PAGE 716
V850ES/JG3-H, V850ES/JH3-H CHAPTER 16 D/A CONVERTER The D/A converter includes the following hardware. Table 16-1. Configuration of D/A Converter Item Configuration D/A converter mode register (DA0M) Control registers D/A conversion value setting registers 0, 1 (DA0CS0, DA0CS1) 16.3 Registers The registers that control the D/A converter are as follows.
PAGE 717
V850ES/JG3-H, V850ES/JH3-H CHAPTER 16 D/A CONVERTER (2) D/A conversion value setting registers 0, 1 (DA0CS0, DA0CS1) The DA0CS0 and DA0CS1 registers set the analog voltage value output to the ANO0 and ANO1 pins. These registers can be read or written in 8-bit units. Reset sets these registers to 00H. After reset: 00H DA0CSn Caution R/W Address: DA0CS0 FFFFF280H, DA0CS1 FFFFF281H DA0CSn7 DA0CSn6 DA0CSn5 DA0CSn4 DA0CSn3 DA0CSn2 DA0CSn1 DA0CSn0 In the real-time output mode (DA0M.
PAGE 718
V850ES/JG3-H, V850ES/JH3-H CHAPTER 16 D/A CONVERTER 16.4 Operation 16.4.1 Operation in normal mode D/A conversion is performed using a write operation to the DA0CSn register as the trigger. The setting method is described below. <1> Set the DA0M.DA0MDn bit to 0 (normal mode). <2> Set the analog voltage value to be output to the ANOn pin to the DA0CSn register. Steps <1> and <2> above constitute the initial settings. <3> Set the DA0M.DA0CEn bit to 1 (D/A conversion enable).
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 16 D/A CONVERTER 16.4.3 Cautions Observe the following cautions when using the D/A converter of the V850ES/JG3-H and V850ES/JH3-H. (1) Do not change the set value of the DA0CSn register while the trigger signal is being issued in the real-time output mode. (2) Before changing the operation mode, be sure to clear the DA0M.DA0CEn bit to 0.
PAGE 720
V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) The V850ES/JG3-H and V850ES/JH3-H have a 5-channel UARTC. 17.
PAGE 721
V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 17.2 Configuration The block diagram of the UARTCn is shown below. Figure 17-1.
PAGE 722
V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) (1) UARTCn control register 0 (UCnCTL0) The UCnCTL0 register is an 8-bit register used to specify the UARTCn operation. (2) UARTCn control register 1 (UCnCTL1) The UCnCTL1 register is an 8-bit register used to select the input clock for the UARTCn. (3) UARTCn control register 2 (UCnCTL2) The UCnCTL2 register is an 8-bit register used to control the baud rate for the UARTCn.
PAGE 723
V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 17.3 Mode Switching Between UARTC and Other Serial Interfaces 17.3.1 Mode switching between UARTC0 and CSIF4 In the V850ES/JG3-H and V850ES/JH3-H, CSIF4 and UARTC0 share the same pins and therefore cannot be used simultaneously. Set UARTC0 in advance, using the PMC3 and PFC3 registers, before use.
PAGE 724
V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 17.3.2 Mode switching between UARTC1 and I2C02 In the V850ES/JG3-H and V850ES/JH3-H, UARTC1 and I2C02 share the same pins and therefore cannot be used simultaneously. Set UARTC1 in advance, using the PMC9, PFC9 and PFCE9 registers, before use. Caution The transmit/receive operation of UARTC1 and I2C02 is not guaranteed if these functions are switched during transmission or reception. Be sure to disable the one that is not used.
PAGE 725
V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 17.3.3 Mode switching between UARTC2 and CSIF3 In the V850ES/JG3-H and V850ES/JH3-H, UARTC2 and CSIF3 share of the same pin and therefore cannot be used simultaneously. Set UARTC2 in advance, using the PMC9, PFC9 and PFCE9 registers, before use. Caution The transmit/receive operation of UARTC2 and CSIF3 is not guaranteed if these functions are switched during transmission or reception.
PAGE 726
V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 17.3.4 Mode switching between UARTC3, I2C00 and CAN0 In the V850ES/JG3-H and V850ES/JH3-H, UARTC3, I2C00, and CAN0 (μPD70F3770, 70F3771 only) share the same pins and therefore cannot be used simultaneously. Set UARTC3 in advance, using the PMC3, PFC3 and PFCE3 registers, before use.
PAGE 727
V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 17.3.5 Mode switching between UARTC4, CSIF0, and I2C01 In the V850ES/JG3-H and V850ES/JH3-H, UARTC4, CSIF0, and I2C01 share the same pin and therefore cannot be used simultaneously. Set UARTC4 in advance, using the PMC4, PFC4, and PMCE4 registers, before use. Caution The transmit/receive operation of UARTC4, CSIF0, and I2C01 is not guaranteed if these functions are switched during transmission or reception.
PAGE 728
V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 17.4 Registers (1) UARTCn control register 0 (UCnCTL0) The UCnCTL0 register is an 8-bit register that controls the UARTCn serial transfer operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 10H.
PAGE 729
V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) (2/2) UCnDIR Transfer direction selection 0 MSB-first transfer 1 LSB-first transfer • This register can be rewritten only when the UCnPWR bit = 0 or the UCnTXE bit = the UCnRXE bit = 0. • When transmission and reception are performed in the LIN format, set the UCnDIR bit to 1.
PAGE 730
V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) (4) UARTCn option control register 0 (UCnOPT0) The UCnOPT0 register is an 8-bit register that controls the serial transfer operation of the UARTCn register. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 14H.
PAGE 731
V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) (2/2) UCnSLS2 UCnSLS1 UCnSLS0 SBF transmission length selection 1 0 1 13-bit output (reset value) 1 1 0 14-bit output 1 1 1 15-bit output 0 0 0 16-bit output 0 0 1 17-bit output 0 1 0 18-bit output 0 1 1 19-bit output 1 0 0 20-bit output This register can be set when the UCnPWR bit = 0 or when the UCnTXE bit = 0.
PAGE 732
V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) (5) UARTCn option control register 1 (UCnOPT1) The UCnOPT1 register is an 8-bit register that controls the serial transfer operation of UARTCn. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. Caution Set the UCnEBE bit while the operation of UARTC is disabled (UCnCTL0.UCnPWR = 0).
PAGE 733
V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) Table 17-2.
PAGE 734
V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) (6) UARTCn status register (UCnSTR) The UCnSTR register is an 8-bit register that displays the UARTCn transfer status and reception error contents. This register can be read or written in 8-bit or 1-bit units, but the UCnTSF bit is a read-only bit, while the UCnPE, UCnFE, and UCnOVE bits can both be read and written.
PAGE 735
V850ES/JG3-H, V850ES/JH3-H After reset: 00H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) R/W Address: UC0STR FFFFFA04H, UC1STR FFFFFA14H, UC2STR FFFFFA24H, UC3STR FFFFFA34H, UC4STR FFFFFA44H UCnSTR <7> 6 5 4 3 <2> <1> <0> UCnTSF 0 0 0 0 UCnPE UCnFE UCnOVE (n = 0 to 4) UCnTSF Transfer status flag 0 • When the UCnPWR bit = 0 or the UCnTXE bit = 0 has been set.
PAGE 736
V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) (7) UARTCn receive data register L (UCnRXL) and UARTCn receive data register (UCnRX) The UCnRXL and UCnRX register are an 8- bit or 9-bit buffer register that stores parallel data converted by the receive shift register. The data stored in the receive shift register is transferred to the UCnRXL and UCnRX register upon completion of reception of 1 byte of data.
PAGE 737
V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) (8) UARTCn transmit data register L (UCnTXL), UARTCn transmit data register (UCnTX) The UCnTXL and UCnTX register is an 8-bit or 9-bit register used to set transmit data. During LSB-first transmission when the data length has been specified as 7 bits, the transmit data is transferred to bits 6 to 0 of the UCnRX register. During MSB-first transmission, the receive data is transferred to bits 7 to 1 of the UCnRX register.
PAGE 738
V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 17.5 Interrupt Request Signals The following two interrupt request signals are generated from UARTCn. • Reception completion interrupt request signal (INTUCnR) • Transmission enable interrupt request signal (INTUCnT) The default priority for these two interrupt request signals is reception completion interrupt request signal then transmission enable interrupt request signal. Table 17-3.
PAGE 739
V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 17.6 Operation 17.6.1 Data format Full-duplex serial data reception and transmission is performed. As shown in Figure 17-7, one data frame of transmit/receive data consists of a start bit, character bits, parity bit, and stop bit(s).
PAGE 740
V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) Figure 17-7.
PAGE 741
V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 17.6.2 SBF transmission/reception format The V850ES/JG3-H and V850ES/JH3-H have an SBF (Sync Break Field) transmission/reception control function to enable use of the LIN function. Remark LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network.
PAGE 742
V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) Figure 17-9. LIN Reception Manipulation Outline Wake-up signal frame Sync break field Sync field Identifier field DATA field Note 2 13 bits SF reception ID reception Data transmission DATA field Check SUM field LIN bus RXDCn (input) SBF reception Enable Disable Data Note 5 transmission Data transmission Note 3 Reception interrupt (INTUCnR) Note 1 Edge detection Note 4 Capture timer Disable Enable Notes 1.
PAGE 743
V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 17.6.3 SBF transmission When the UCnCTL0.UCnPWR bit = UCnCTL0.UCnTXE bit = 1, the transmission enabled status is entered, and SBF transmission is started by setting (to 1) the SBF transmission trigger (UCnOPT0.UCnSTT bit). Thereafter, a low level the width of bits 13 to 20 specified by the UCnOPT0.UCnSLS2 to UCnOPT0.UCnSLS0 bits is output.
PAGE 744
V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 17.6.4 SBF reception The reception wait status is entered by setting the UCnCTL0.UCnPWR bit to 1 and then setting the UCnCTL0.UCnRXE bit to 1. The SBF reception wait status is set by setting the SBF reception trigger (UCnOPT0.UCnSRT bit) to 1. In the SBF reception wait status, similarly to the UART reception wait status, the RXDCn pin is monitored and start bit detection is performed.
PAGE 745
V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 17.6.5 UART transmission A high level is output to the TXDCn pin by setting the UCnCTL0.UCnPWR bit to 1. Next, the transmission enabled status is set by setting the UCnCTL0.UCnTXE bit to 1, and transmission is started by writing transmit data to the UCnTX register. The start bit, parity bit, and stop bit are automatically added.
PAGE 746
V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 17.6.6 Continuous transmission procedure UARTCn can write the next transmit data to the UCnTX register when the UARTCn transmit shift register starts the shift operation. The transmit timing of the UARTCn transmit shift register can be judged from the transmission enable interrupt request signal (INTUCnT).
PAGE 747
V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) Figure 17-14.
PAGE 748
V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 17.6.7 UART reception The reception wait status is set by setting the UCnCTL0.UCnPWR bit to 1 and then setting the UCnCTL0.UCnRXE bit to 1. In the reception wait status, the RXDCn pin is monitored and start bit detection is performed. Start bit detection is performed using a two-step detection routine. First the rising edge of the RXDCn pin is detected and sampling is started at the falling edge.
PAGE 749
V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 17.6.8 Reception errors Errors during a receive operation are of three types: parity errors, framing errors, and overrun errors. Data reception result error flags are set in the UCnSTR register and a reception completion interrupt request signal (INTUCnR) is output when an error occurs. It is possible to ascertain which error occurred during reception by reading the contents of the UCnSTR register.
PAGE 750
V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) • Reception error causes Error Flag Reception Error Cause UCnPE Parity error Received parity bit does not match the setting UCnFE Framing error Stop bit not detected UCnOVE Overrun error Reception of next data completed before data was read from receive buffer When reception errors occur, perform the following procedures depending upon the kind of error.
PAGE 751
V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 17.6.9 Parity types and operations Caution When using the LIN function, fix the UCnCTL0.UCnPS1 and UCnCTL0.UCnPS0 bits to 00. The parity bit is used to detect bit errors in the communication data. Normally the same parity is used on the transmission side and the reception side. In the case of even parity and odd parity, it is possible to detect odd-count bit errors.
PAGE 752
V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 17.6.10 Receive data noise filter This filter samples the RXDCn pin using the base clock of the prescaler output. When the same sampling value is read twice, the match detector output changes and the RXDCn signal is sampled as the input data. Therefore, data not exceeding 2 clock width is judged to be noise and is not delivered to the internal circuit (see Figure 17-18). See 17.7 (1) (a) Base clock regarding the base clock.
PAGE 753
V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 17.7 Dedicated Baud Rate Generator The dedicated baud rate generator consists of a source clock selector block and an 8-bit programmable counter, and generates a serial clock during transmission and reception with UARTCn. Regarding the serial clock, a dedicated baud rate generator output can be selected for each channel. There is an 8-bit counter for transmission and another one for reception.
PAGE 754
V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) (2) UARTCn control register 1 (UCnCTL1) The UCnCTL1 register is an 8-bit register that selects the UARTCn base clock. This register can be read or written in 8-bit units. Reset sets this register to 00H. Caution Clear the UCnCTL0.UCnPWR bit to 0 before rewriting the UCnCTL1 register.
PAGE 755
V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) (3) UARTCn control register 2 (UCnCTL2) The UCnCTL2 register is an 8-bit register that selects the baud rate (serial transfer speed) clock of UARTCn. This register can be read or written in 8-bit units. Reset sets this register to FFH. Caution Clear the UCnCTL0.UCnPWR bit to 0 or clear the UCnTXE and UCnRXE bits to 00 before rewriting the UCnCTL2 register.
PAGE 756
V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) (4) Baud rate The baud rate is obtained by the following equation. Baud rate = fUCLK [bps] 2×k When using the internal clock, the equation will be as follows (when using the ASCKC0 pin as clock at UARTC0, calculate using the above equation). Baud rate = fXX m+1 2 Remark ×k [bps] fUCLK = Frequency of base clock selected by the UCnCTL1.UCnCKS3 to UCnCTL1.
PAGE 757
V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) To set the baud rate, perform the following calculation for setting the UCnCTL1 and UCnCTL2 registers (when using internal clock). <1> Set k to fxx/2/(2 × target baud rate) and m to 0. <2> If k is 256 or greater (k ≥ 256), reduce k to half (k/2) and increment m by 1 (m + 1). <3> Repeat Step <2> until k becomes less than 256 (k < 256). <4> Round off the first decimal point of k to the nearest whole number.
PAGE 758
V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) (5) Allowable baud rate range during reception The baud rate error range at the destination that is allowable during reception is shown below. Caution The baud rate error during reception must be set within the allowable error range using the following equation. Figure 17-20.
PAGE 759
V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) Therefore, the maximum baud rate that can be received by the destination is as follows. BRmax = (FLmin/11)−1 = 22k Brate 21k + 2 Similarly, obtaining the following maximum allowable transfer rate yields the following. 10 k+2 × FLmax = 11 × FL − 2×k 11 FLmax = 21k − 2 × FL = 21k − 2 2×k FL FL × 11 20 k Therefore, the minimum baud rate that can be received by the destination is as follows.
PAGE 760
V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) (6) Transfer rate during continuous transmission During continuous transmission, the transfer rate from the stop bit to the next start bit is usually 2 base clocks longer. However, timing initialization is performed via start bit detection by the receiving side, so this has no influence on the transfer result. Figure 17-21.
PAGE 761
V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 17.8 Cautions (1) When the clock supply to UARTCn is stopped (for example, in IDLE1, IDLE2, or STOP mode), the operation stops with each register retaining the value it had immediately before the clock supply was stopped. The TXDCn pin output also holds and outputs the value it had immediately before the clock supply was stopped. However, the operation is not guaranteed after the clock supply is resumed.
PAGE 762
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 18.1 Mode Switching of CSIF and Other Serial Interfaces 18.1.1 CSIF4 and UARTC0 mode switching In the V850ES/JG3-H and V850ES/JH3-H, CSIF4 and UARTC0 share the same pins and therefore cannot be used simultaneously. To use CSIF4, the use of CSIF4 must be set in advance, using the PMC3, PFC3 and PFCE3 registers.
PAGE 763
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 2 18.1.2 CSIF0, UARTC4, and I C01 mode switching In the V850ES/JG3-H and V850ES/JH3-H, CSIF0, UARTC4, and I2C01 share the same pins and therefore cannot be used simultaneously. Switching among CSIF0, UARTC4, and I2C01 must be set in advance, using the PMC4, PFC4, and PFCE4 registers.
PAGE 764
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 18.1.3 CSIF3 and UARTC2 mode switching In the V850ES/JG3-H and V850ES/JH3-H, CSIF3 and UARTC2 share the same pins and therefore cannot be used simultaneously. Switching between CSIF3 and UARTC2 must be set in advance, using the PMC9, PFC9 and PFCE9 registers. Caution The transmit/receive operation of CSIF3 and UARTC2 is not guaranteed if these functions are switched during transmission or reception.
PAGE 765
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 18.2 Features { Transfer rate: 12 Mbps max.
PAGE 766
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 18.3 Configuration The following shows the block diagram of CSIFn. Figure 18-4.
PAGE 767
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) CSIFn includes the following hardware. Table 18-1. Configuration of CSIFn Item Configuration CSIFn receive data register (CFnRX) Registers CSIFn transmit data register (CFnTX) CSIFn control register 0 (CFnCTL0) CSIFn control register 1 (CFnCTL1) CSIFn control register 2 (CFnCTL2) CSIFn status register (CFnSTR) (1) CSIFn receive data register (CFnRX) The CFnRX register is a 16-bit buffer register that holds receive data.
PAGE 768
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (2) CSIFn transmit data register (CFnTX) The CFnTX register is a 16-bit buffer register used to write the CSIFn transfer data. This register can be read or written in 16-bit units. The transmit operation is started by writing data to the CFnTX register in the transmission enabled status. If the transfer data length is 8 bits, the lower 8 bits of this register are read-only in 8-bit units as the CFnTXL register.
PAGE 769
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 18.4 Registers The following registers are used to control CSIFn. • CSIFn control register 0 (CFnCTL0) • CSIFn control register 1 (CFnCTL1) • CSIFn control register 2 (CFnCTL2) • CSIFn status register (CFnSTR) (1) CSIFn control register 0 (CFnCTL0) CFnCTL0 is a register that controls the CSIFn serial transfer operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 01H.
PAGE 770
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (2/3) CFnDIRNote Specification of transfer direction mode (MSB/LSB) 0 MSB-first transfer 1 LSB-first transfer CFnTMSNote Transfer mode specification 0 Single transfer mode 1 Continuous transfer mode [In single transfer mode] The reception completion interrupt (INTCFnR) occurs when communication is complete. Even if transmission is enabled (CFnTXE bit = 1), the transmission enable interrupt (INTCFnT) does not occur.
PAGE 771
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (3/3) CFnSCE Specification of start transfer disable/enable 0 Communication start trigger invalid 1 Communication start trigger valid • In master mode This bit enables or disables the communication start trigger.
PAGE 772
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (2) CSIFn control register 1 (CFnCTL1) CFnCTL1 is an 8-bit register that controls the CSIFn serial transfer operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. Caution The CFnCTL1 register can be rewritten only when the CFnCTL0.CFnPWR bit = 0.
PAGE 773
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (3) CSIFn control register 2 (CFnCTL2) CFnCTL2 is an 8-bit register that controls the number of CSIFn serial transfer bits. This register can be read or written in 8-bit units. Reset sets this register to 00H. Caution The CFnCTL2 register can be rewritten only when the CFnCTL0.CFnPWR bit = 0 or when both the CFnTXE and CFnRXE bits = 0.
PAGE 774
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (a) Transfer data length change function The CSIFn transfer data length can be set in 1-bit units between 8 and 16 bits using the CFnCTL2.CFnCL3 to CFnCTL2.CFnCL0 bits. When the transfer bit length is set to a value other than 16 bits, set the data to the CFnTX or CFnRX register starting from the LSB, regardless of whether the transfer start bit is the MSB or LSB.
PAGE 775
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (4) CSIFn status register (CFnSTR) CFnSTR is an 8-bit register that displays the CSIFn status. This register can be read or written in 8-bit or 1-bit units, but the CFnTSF flag is read-only. Reset sets this register to 00H. In addition to reset input, the CFnSTR register can be initialized by clearing (0) the CFnCTL0.CFnPWR bit.
PAGE 776
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 18.5 Interrupt Request Signals CSIFn can generate the following two types of interrupt request signals. • Reception completion interrupt request signal (INTCFnR) • Transmission enable interrupt request signal (INTCFnT) Of these two interrupt request signals, the reception completion interrupt request signal has the higher priority by default, and the priority of the transmission enable interrupt request signal is lower.
PAGE 777
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 18.6 Operation 18.6.1 Single transfer mode (master mode, transmission mode) MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00), communication clock (fCCLK) = fXX/2 or fXX/3 (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 000), transfer data length = 8 bits (CFnCTL2.CFnCL3 to CFnCTL2.
PAGE 778
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (2) Operation timing CFnTSF bit INTCFnR signal SCKFn pin SOFn pin Bit 7 (1) (2) (3) (4) Bit 6 Bit 5 Bit 4 Bit 3 (5) Bit 2 Bit 1 Bit 0 (6) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (7) Bit 0 (8) (1) Write 00H to the CFnCTL1 register, and select communication type 1, communication clock (fCCLK) = fXX/2 or fXX/3, and master mode.
PAGE 779
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 18.6.2 Single transfer mode (master mode, reception mode) MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00), communication clock (fCCLK) = fXX/2 or fXX/3 (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 000), transfer data length = 8 bits (CFnCTL2.CFnCL3 to CFnCTL2.
PAGE 780
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (2) Operation timing CFnTSF bit INTCFnR signal SCKFn pin SIFn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIFn pin capture timing (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (1) Write 00H to the CFnCTL1 register, and select communication type 1, communication clock (fCCLK) = fXX/2 or fXX/3, and master mode.
PAGE 781
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 18.6.3 Single transfer mode (master mode, transmission/reception mode) MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00), communication clock (fCCLK) = fXX/2 or fXX/3 (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 000), transfer data length = 8 bits (CFnCTL2.CFnCL3 to CFnCTL2.
PAGE 782
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (2) Operation timing CFnTSF bit INTCFnR signal SCKFn pin SOFn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIFn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIFn pin capture timing (1) (2) (3) (4) (5) (6) (7) (8) (9)(10) (1) Write 00H to the CFnCTL1 register, and select communicati
PAGE 783
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 18.6.4 Single transfer mode (slave mode, transmission mode) MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00), communication clock (fCCLK) = external clock (SCKFn) (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 111), transfer data length = 8 bits (CFnCTL2.CFnCL3 to CFnCTL2.
PAGE 784
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (2) Operation timing CFnTSF bit INTCFnR signal SCKFn pin SOFn pin Bit 7 (1) (2) (3) (4) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (5) Bit 0 (6) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (7) Bit 0 (8) (1) Write 07H to the CFnCTL1 register, and select communication type 1, communication clock (fCCLK) = external clock (SCKFn), and slave mode.
PAGE 785
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 18.6.5 Single transfer mode (slave mode, reception mode) MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00), communication clock (fCCLK) = external clock (SCKFn) (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 111), transfer data length = 8 bits (CFnCTL2.CFnCL3 to CFnCTL2.
PAGE 786
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (2) Operation timing CFnTSF bit INTCFnR signal SCKFn pin SIFn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIFn pin capture timing (4) (1) (2) (3) (5) (6) (7) (8) (9) (10) (1) Write 07H to the CFnCTL1 register, and select communication type 1, communication clock (fCCLK) = external clock (SCKFn), and slave mode.
PAGE 787
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 18.6.6 Single transfer mode (slave mode, transmission/reception mode) MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00), communication clock (fCCLK) = external clock (SCKFn) (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 111), transfer data length = 8 bits (CFnCTL2.CFnCL3 to CFnCTL2.
PAGE 788
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (2) Operation timing CFnTSF bit INTCFnR signal SCKFn pin SOFn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIFn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIFn pin capture timing (1) (2) (3) (4) (5) (6) (7) (8) (9)(10) (1) Write 07H to the CFnCTL1 register, and select communi
PAGE 789
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 18.6.7 Continuous transfer mode (master mode, transmission mode) MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00), communication clock (fCCLK) = fXX/2 or fXX/3 (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 000), transfer data length = 8 bits (CFnCTL2.CFnCL3 to CFnCTL2.
PAGE 790
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (2) Operation timing CFnTSF bit INTCFnT signal INTCFnR signal L SCKFn pin SOFn pin Bit 7 (1) (2) (3) (4) (5) Bit 6 (6) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (7) Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (8) (9) (10) (11) (1) Write 00H to the CFnCTL1 register, and select communication type 1, communication clock (fCCLK) = fXX/2 or fXX/3, and master mode.
PAGE 791
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 18.6.8 Continuous transfer mode (master mode, reception mode) MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00), communication clock (fCCLK) = fXX/2 or fXX/3 (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 000), transfer data length = 8 bits (CFnCTL2.CFnCL3 to CFnCTL2.CFnCL0 bits = 0000) R01UH0042EJ0500 Rev.5.
PAGE 792
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (1) Operation flow START (1), (2), (3) CFnCTL1 register ← 00H CFnCTL2 register ← 00H CFnCTL0 register ← A3H (4) CFnRX register dummy read (5) Start reception No INTCFnR interrupt generated? Yes CFnOVE bit = 1? (CFnSTR) No (6) Yes (8) Is data being received last data? CFnSCE bit = 0 (CFnCTL0) No (7) Yes (9) Read CFnRX register (12) CFnOVE bit = 0 (CFnSTR) (8) CFnSCE bit = 0 (CFnCTL0) (9) (9) Read CFnRX re
PAGE 793
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (2) Operation timing CFnTSF bit INTCFnR signal CFnSCE bit SCKFn pin SOFn pin L SIFn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIFn pin capture timing (1) (3) (4) (2) (5) (6) (7) (8) (9) (10) (11) (13) (1) Write 00H to the CFnCTL1 register, and select communication type 1, communication clock (fCCLK) = fXX/2, and master mode.
PAGE 794
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 18.6.9 Continuous transfer mode (master mode, transmission/reception mode) MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00), communication clock (fCCLK) = fXX/2 or fXX/3 (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 000), transfer data length = 8 bits (CFnCTL2.CFnCL3 to CFnCTL2.CFnCL0 bits = 0000) R01UH0042EJ0500 Rev.5.
PAGE 795
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (1) Operation flow START (1), (2), (3) CFnCTL1 register ← 00H CFnCTL2 register ← 00H CFnCTL0 register ← E3H (4) Write CFnTX register (5) Start transmission/reception (6), (11) INTCFnT interrupt generated? No Yes (7) Is data being transmitted last data? Yes (11) No (7) No Write CFnTX register INTCFnR interrupt generated? (8) Yes No (9) CFnOVE bit = 1? (CFnSTR) (10) Read CFnRX register Yes (13) (13) Read C
PAGE 796
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (2) Operation timing (1/2) CFnTSF bit INTCFnT signal INTCFnR signal SCKFn pin SOFn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIFn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIFn pin capture timing (4) (1) (2) (3) (5) (6) (7) (8) (9) (10) (11) (12) (13) (15) (1) Write 00H
PAGE 797
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (2/2) (11) The transfer of the transmit data from the CFnTX register to the shift register is completed and the INTCFnT signal is generated. To end continuous transmission/reception with the current transmission/reception, do not write to the CFnTX register.
PAGE 798
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 18.6.10 Continuous transfer mode (slave mode, transmission mode) MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00), communication clock (fCCLK) = external clock (SCKFn) (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 111), transfer data length = 8 bits (CFnCTL2.CFnCL3 to CFnCTL2.
PAGE 799
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (2) Operation timing CFnTSF bit INTCFnT signal SCKFn pin SOFn pin Bit 7 (1) (2) (3) (4) (5) Bit 6 (6) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (7) Bit 0 Bit 7 (8) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (9) Bit 0 (10) (11) (1) Write 07H to the CFnCTL1 register, and select communication type 1, communication clock (fCCLK) = external clock (SCKFn), and slave mode.
PAGE 800
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 18.6.11 Continuous transfer mode (slave mode, reception mode) MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00), communication clock (fCCLK) = external clock (SCKFn) (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 111), transfer data length = 8 bits (CFnCTL2.CFnCL3 to CFnCTL2.CFnCL0 bits = 0000) R01UH0042EJ0500 Rev.5.
PAGE 801
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (1) Operation flow START (1), (2), (3) CFnCTL1 register ← 07H CFnCTL2 register ← 00H CFnCTL0 register ← A3H (4) CFnRX register dummy read (4) SCKFn pin input started? No Yes (5) Reception start No INTCFnR interrupt generated? Yes CFnOVE bit = 1? (CFnSTR) No (6) Yes CFnSCE bit = 0 (CFnCTL0) (8) (9) Is data being received last data? Read CFnRX register (7) Yes (8) CFnOVE bit = 0 (CFnSTR) (12) No CFnSCE b
PAGE 802
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (2) Operation timing CFnTSF bit INTCFnR signal CFnSCE bit SCKFn pin SIFn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIFn pin capture timing (1) (3) (4) (2) (5) (6) (7) (8) (9) (10) (11) (13) (1) Write 07H to the CFnCTL1 register, and select communication type 1, communication clock (fCCLK) = external clock (SCKFn), and slave mode.
PAGE 803
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 18.6.12 Continuous transfer mode (slave mode, transmission/reception mode) MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00), communication clock (fCCLK) = external clock (SCKFn) (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 111), transfer data length = 8 bits (CFnCTL2.CFnCL3 to CFnCTL2.CFnCL0 bits = 0000) R01UH0042EJ0500 Rev.5.
PAGE 804
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (1) Operation flow START (1), (2), (3) CFnCTL1 register ← 07H CFnCTL2 register ← 00H CFnCTL0 register ← E3H (4) Write CFnTX register (4) SCKFn pin input started? No Yes (5) (6), (11) Start transmission/reception INTCFnT interrupt generated? No Yes (7) Is data being transmitted last data? Yes (11) No (7) No Write CFnTX register INTCFnR interrupt generated? (8) Yes No (9) CFnOVE bit = 1? (CFnSTR) (10) Y
PAGE 805
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (2) Operation timing (1/2) CFnTSF bit INTCFnT signal INTCFnR signal SCKFn pin SOFn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIFn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIFn pin capture timing (4) (1) (2) (3) (5) (6) (7) (8) (9) (10) (11) (12) (13) (15) (1) Write 07H t
PAGE 806
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (2/2) (12) When the clock of the transfer data length set with the CFnCTL2 register is input without writing to the CFnTX register, the INTCFnR signal is generated. Clear the CFnTSF bit to 0 to end transmission/reception. (13) When the INTCFnR signal is generated, read the CFnRX register. (14) If an overrun error occurs, write CFnSTR.CFnOVE bit = 0, and clear the error flag.
PAGE 807
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 18.6.13 Reception error When transfer is performed with reception enabled (CFnCTL0.CFnRXE bit = 1) in the continuous transfer mode, the reception completion interrupt request signal (INTCFnR) is generated again when the next receive operation is completed before the CFnRX register is read after the INTCFnR signal is generated, and the overrun error flag (CFnSTR.CFnOVE) is set to 1.
PAGE 808
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 18.6.14 Clock timing (1/2) (i) Communication type 1 (CFnCKP and CFnDAP bits = 00) SCKFn pin SIFn capture SOFn pin D7 D6 D5 D4 D3 D2 D1 D0 Reg-R/W INTCFnT interruptNote 1 INTCFnR interruptNote 2 CFnTSF bit (ii) Communication type 3 (CFnCKP and CFnDAP bits = 10) SCKFn pin SIFn capture SOFn pin D7 D6 D5 D4 D3 D2 D1 D0 Reg-R/W INTCFnT interruptNote 1 INTCFnR interruptNote 2 CFnTSF bit Notes 1.
PAGE 809
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (2/2) (iii) Communication type 2 (CFnCKP and CFnDAP bits = 01) SCKFn pin SIFn capture D7 SOFn pin D6 D5 D4 D3 D2 D1 D0 Reg-R/W INTCFnT interruptNote 1 INTCFnR interruptNote 2 CFnTSF bit (iv) Communication type 4 (CFnCKP and CFnDAP bits = 11) SCKFn pin SIFn capture SOFn pin D7 D6 D5 D4 D3 D2 D1 D0 Reg-R/W INTCFnT interruptNote 1 INTCFnR interruptNote 2 CFnTSF bit Notes 1.
PAGE 810
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 18.7 Output Pins (1) SCKFn pin When CSIFn operation is disabled (CFnCTL0.CFnPWR bit = 0), the SCKFn pin output status is as follows. CFnCKP CFnCKS2 CFnCKS1 CFnCKS0 0 1 1 1 Other than above 1 1 1 High impedance Fixed to high level 1 Other than above SCKFn Pin Output High impedance Fixed to low level Remarks 1. The output level of the SCKFn pin changes if any of the CFnCTL1.
PAGE 811
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 18.8 Baud Rate Generator The BRG1 to BRG3 baud rate generators are connected to CSIF0 to CSIF4 as shown in the following block diagram. fXX BRG1 fBRG1 CSIF0 CSIF1 fXX BRG2 fBRG2 CSIF2 CSIF3 fXX BRG3 fBRG3 CSIF4 (1) Prescaler mode registers 1 to 3 (PRSM1 to PRSM3) The PRSM1 to PRSM3 registers control generation of the baud rate signal for CSIF. These registers can be read or written in 8-bit or 1-bit units.
PAGE 812
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (2) Prescaler compare registers 1 to 3 (PRSCM1 to PRSCM3) The PRSCM1 to PRSCM3 registers are 8-bit compare registers. These registers can be read or written in 8-bit units. Reset sets these registers to 00H. After reset: 00H R/W Address: PRSCM1 FFFFF321H, PRSCM2 FFFFF325H, PRSCM3 FFFFF329H PRSCMm PRSCMm7 PRSCMm6 PRSCMm5 PRSCMm4 PRSCMm3 PRSCMm2 PRSCMm1 PRSCMm0 Cautions 1.
PAGE 813
V850ES/JG3-H, V850ES/JH3-H CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 18.9 Cautions (1) When transferring transmit data and receive data using DMA transfer, error processing cannot be performed even if an overrun error occurs during serial transfer. Check that the no overrun error has occurred by reading the CFnSTR.CFnOVE bit after DMA transfer has been completed. (2) If a register that is prohibited to be rewritten during operation (CFnCTL0.
PAGE 814
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H CHAPTER 19 I2C BUS To use the I2C bus function, set the P36/SCL00, P37/SDA00, P40/SDA01, P41/SCL01, P90/SDA02, and P91/SCL02 pins as alternate-function pins, and set them to N-ch open-drain output. 19.1 Mode Switching of I2C Bus and Other Serial Interfaces 19.1.1 UARTC3 and I2C00 mode switching In the V850ES/JG3-H and V850ES/JH3-H, UARTC3 and I2C00 share the same pins and therefore cannot be used simultaneously.
PAGE 815
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H 2 19.1.2 UARTC4, CSIF0, and I C01 mode switching In the V850ES/JG3-H and V850ES/JH3-H, UARTC4, CSIF0, and I2C01 share the same pins and therefore cannot be used simultaneously. Switching among UARTC4, CSIF0, and I2C01 must be set in advance, using the PMC4, PFC4, and PFCE4 registers. Caution The transmit/receive operation of UARTC4, CSIF0, and I2C01 is not guaranteed if these functions are switched during transmission or reception.
PAGE 816
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H 2 19.1.3 UARTC1 and I C02 mode switching In the V850ES/JG3-H and V850ES/JH3-H, UARTC1 and I2C02 share the same pins and therefore cannot be used simultaneously. Switching between UARTC1 and I2C02 must be set in advance, using the PMC9, PFC9, and PFCE9 registers. Caution The transmit/receive operation of UARTC1 and I2C02 is not guaranteed if these functions are switched during transmission or reception. Be sure to disable the one that is not used.
PAGE 817
V850ES/JG3-H, V850ES/JH3-H CHAPTER 19 I2C BUS 19.2 Features I2C00 to I2C02 have the following two modes. • Operation stop mode • I2C (Inter IC) bus mode (multimasters supported) (1) Operation stop mode In this mode, serial transfer is not performed, thus enabling a reduction in power consumption. (2) I2C bus mode (multimaster support) This mode is used for 8-bit data transfers with several devices via two lines: a serial clock pin (SCL0n) and a serial data bus pin (SDA0n).
PAGE 818
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H 19.3 Configuration The block diagram of the I2C0n is shown below. Figure 19-4.
PAGE 819
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H A serial bus configuration example is shown below. Figure 19-5. Serial Bus Configuration Example Using I2C Bus +VDD +VDD Master CPU1 SDA Slave CPU1 Address 1 R01UH0042EJ0500 Rev.5.
PAGE 820
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H 2 I C0n includes the following hardware (n = 0 to 2). Table 19-1.
PAGE 821
V850ES/JG3-H, V850ES/JH3-H CHAPTER 19 I2C BUS (7) Interrupt request signal generator This circuit controls the generation of interrupt request signals (INTIICn). An I2C interrupt is generated by either of the following two triggers. • The falling edge of the eighth or ninth clock of the serial clock (set by IICCn.WTIMn bit) • Interrupt occurrence due to stop condition detection (set by IICCn.
PAGE 822
V850ES/JG3-H, V850ES/JH3-H CHAPTER 19 I2C BUS 19.4 Registers I2C00 to I2C02 are controlled by the following registers. • IIC control registers 0 to 2 (IICC0 to IICC2) • IIC status registers 0 to 2 (IICS0 to IICS2) • IIC flag registers 0 to 2 (IICF0 to IICF2) • IIC clock select registers 0 to 2 (IICCL0 to IICCL2) • IIC function expansion registers 0 to 2 (IICX0 to IICX2) • IIC division clock select registers 0, 1 (OCKS0, OCKS1) The following registers are also used.
PAGE 823
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H (1/4) After reset: 00H IICCn R/W Address: IICC0 FFFFFD82H, IICC1 FFFFFD92H, IICC2 FFFFFDA2H <7> <6> <5> <4> <3> <2> <1> <0> IICEn LRELn WRELn SPIEn WTIMn ACKEn STTn SPTn (n = 0 to 2) 2 IICEn Specification of I Cn operation enable/disable 0 Operation stopped. IICSn register reset 1 Operation enabled. Note 1 . Internal operation stopped. Be sure to set this bit to 1 when the SCL0n and SDA0n lines are high level.
PAGE 824
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H (2/4) Note SPIEn Enabling/disabling generation of interrupt request when stop condition is detected 0 Disabled 1 Enabled Condition for clearing (SPIEn bit = 0) Condition for setting (SPIEn bit = 1) • Cleared by instruction • After reset • Set by instruction Note WTIMn Control of wait state and interrupt request generation 0 Interrupt request is generated at the eighth clock’s falling edge.
PAGE 825
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H (3/4) STTn Start condition trigger 0 Start condition is not generated. 1 When bus is released (in STOP mode): A start condition is generated (for starting as master). The SDA0n line is changed from high level to low level while the SCLn line is high level and then the start condition is generated. Next, after the rated amount of time has elapsed, the SCL0n line is changed to low level.
PAGE 826
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H (4/4) SPTn 0 1 Stop condition trigger Stop condition is not generated. Stop condition is generated (termination of master device’s transfer). After the SDA0n line goes to low level, either set the SCL0n line to high level or wait until the SCL0n pin goes to high level. Next, after the rated amount of time has elapsed, the SDA0n line is changed from low level to high level and a stop condition is generated.
PAGE 827
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H (2) IIC status registers 0 to 2 (IICS0 to IICS2) The IICSn registers indicate the status of I2C0n (n = 0 to 2). These registers are read-only, in 8-bit or 1-bit units. However, the IICSn registers can only be read when the IICCn.STTn bit is 1 or during the wait period. Reset sets these registers to 00H. Caution Accessing the IICSn registers is prohibited in the following statuses. For details, see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers.
PAGE 828
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H (2/3) COIn Matching address detection 0 Addresses do not match. 1 Addresses match. Condition for clearing (COIn bit = 0) Condition for setting (COIn bit = 1) • When a start condition is detected • When the received address matches the local • When a stop condition is detected address (SVAn register) (set at the rising edge of the • Cleared by LRELn bit = 1 (communication save) eighth clock).
PAGE 829
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H (3/3) STDn Start condition detection 0 Start condition was not detected. 1 Start condition was detected.
PAGE 830
V850ES/JG3-H, V850ES/JH3-H CHAPTER 19 I2C BUS (3) IIC flag registers 0 to 2 (IICF0 to IICF2) The IICFn registers set the I2C0n operation mode and indicate the I2C bus status. These registers can be read or written in 8-bit or 1-bit units. However, the STCFn and IICBSYn bits are read-only. IICRSVn enables/disables the communication reservation function (see 19.14 Communication Reservation). The initial value of the IICBSYn bit is set by using the STCENn bit (see 19.15 Cautions).
PAGE 831
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H After reset: 00H IICFn R/W Note Address: IICF0 FFFFFD8AH, IICF1 FFFFFD9AH, IICF2 FFFFFDAAH <7> <6> 5 4 3 2 <1> <0> STCFn IICBSYn 0 0 0 0 STCENn IICRSVn (n = 0 to 2) STCFn STTn bit clear 0 Start condition issued 1 Start condition cannot be issued, STTn bit cleared Condition for clearing (STCFn bit = 0) Condition for setting (STCFn bit = 1) • Cleared by IICCn.STTn bit = 1 • When the IICCn.
PAGE 832
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H (4) IIC clock select registers 0 to 2 (IICCL0 to IICCL2) The IICCLn registers set the transfer clock for I2C0n. These registers can be read or written in 8-bit or 1-bit units. However, the CLDn and DADn bits are read-only. Set the IICCLn registers when the IICCn.IICEn bit = 0. The SMCn, CLn1, and CLn0 bits are set by combining the IICXn.CLXn bit and the OCKSTHm, OCKSm1, and OCKSm0 bits of the OCKSm register (see 19.
PAGE 833
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H (5) IIC function expansion registers 0 to 2 (IICX0 to IICX2) The IICXn registers set I2C0n function expansion (valid only in the high-speed mode). These registers can be read or written in 8-bit or 1-bit units. Setting of the CLXn bit is performed in combination with the SMCn, CLn1, and CLn0 bits of the IICCLn register and the OCKSTHm, OCKSm1, and OCKSm0 bits of the OCKSm register (see 19.4 (6) I2C0n transfer clock setting method) (m = 0, 1).
PAGE 834
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H Table 19-2. Clock Settings IICXn IICCLn Selection Clock CLXn SMCn CLn1 CLn0 0 0 0 0 Transfer Clock Settable Main Clock Frequency (fXX) Range Transfer Speed Operating Mode fxx/6 (OCKSm = 11H) fxx/264 24.00 MHz ≤ fxx ≤ 25.14 MHz 90.91 kHz to 95.23 kHz Standard fxx/8 (OCKSm= 12H) fxx/352 24.00 MHz ≤ fxx ≤ 33.52 MHz 68.18 kHz to 95.23 kHz mode (SMCn = 0) fxx/10 (OCKSm = 13H) fxx/440 30.00 MHz ≤ fxx ≤ 41.90 MHz 68.18 kHz to 95.
PAGE 835
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H (7) IIC division clock select registers 0, 1 (OCKS0, OCKS1) The OCKSm registers control the I2C0n division clock (n = 0 to 2, m = 0, 1). These registers control the I2C00 division clock via the OCKS0 register and the I2C01 and I2C02 division clocks via the OCKS1 register. These registers can be read or written in 8-bit units. Reset sets these registers to 00H.
PAGE 836
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H (9) Slave address registers 0 to 2 (SVA0 to SVA2) The SVAn registers hold the I2C bus’s slave address. These registers can be read or written in 8-bit units, but bit 0 should be fixed to 0. However, rewriting these registers is prohibited when the IICSn.STDn bit = 1 (start condition detection). Reset sets these registers to 00H.
PAGE 837
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H 19.5 I2C Bus Mode Functions 19.5.1 Pin configuration The serial clock pin (SCL0n) and serial data bus pin (SDA0n) are configured as follows (n = 0 to 2). SCL0n .................This pin is used for serial clock input and output. This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input. SDA0n ................This pin is used for serial data input and output.
PAGE 838
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H 19.6 I2C Bus Definitions and Control Methods The following section describes the I2C bus’s serial data communication format and the signals used by the I2C bus. The transfer timing for the “start condition”, “address”, “transfer direction specification”, “data”, and “stop condition” generated on the I2C bus’s serial data bus is shown below. Figure 19-7.
PAGE 839
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H 19.6.2 Addresses The 7 bits of data that follow the start condition are defined as an address. An address is a 7-bit data segment that is output so that the master device can select one of the slave devices that are connected to the bus lines. Therefore, each slave device connected via the bus lines must have a unique address.
PAGE 840
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H 19.6.3 Transfer direction specification In addition to the 7-bit address data, the master device sends 1 bit of data that specifies the transfer direction. When this transfer direction specification bit has a value of 0, it indicates that the master device is transmitting data to a slave device. When the transfer direction specification bit has a value of 1, it indicates that the master device is receiving data from a slave device. Figure 19-10.
PAGE 841
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H 19.6.4 ACK ACK is used to confirm the serial data status of the transmitting and receiving devices. The receiving device returns ACK for every 8 bits of data it receives. The transmitting device normally receives ACK after transmitting 8 bits of data. When ACK is returned from the receiving device, the reception is judged as normal and processing continues. The detection of ACK is confirmed using the IICSn.ACKDn bit.
PAGE 842
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H 19.6.5 Stop condition When the SCL0n pin is high level, changing the SDA0n pin from low level to high level generates a stop condition (n = 0 to 2). A stop condition is generated when serial transfer from the master device to the slave device has been completed. When the V850ES/JG3-H or V850ES/JH3-H is used as the slave device, it can detect the stop condition. Figure 19-12.
PAGE 843
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H 19.6.6 Wait state A wait state is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCL0n pin to low level notifies the communication partner of the wait state. When the wait state has been canceled for both the master and slave devices, the next data transfer can begin (n = 0 to 2). Figure 19-13.
PAGE 844
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H Figure 19-13. Wait State (2/2) (b) When master and slave devices are both in a nine-clock wait state (master: transmission, slave: reception, and ACKEn bit = 1) Master and slave both wait after output of ninth clock. IICn data write (cancel wait state) Master IICn 6 SCL0n 7 8 1 9 2 3 Slave FFH is written to IICn register or WRELn bit is set to 1.
PAGE 845
V850ES/JG3-H, V850ES/JH3-H CHAPTER 19 I2C BUS 19.6.7 Wait state cancellation method In the case of I2C0n, a wait state can be canceled normally in the following ways (n = 0 to 2). • By writing data to the IICn register • By setting the IICCn.WRELn bit to 1 (wait state cancellation) • By setting the IICCn.STTn bit to 1 (start condition generation) • By setting the IICCn.
PAGE 846
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H 19.7 I2C Interrupt Request Signals (INTIICn) The following shows the value of the IICSn register at the INTIICn interrupt request signal generation timing and at the INTIICn signal timing (n = 0 to 2). 19.7.1 Master device operation (1) Start ~ Address ~ Data ~ Data ~ Stop (normal transmission/reception) <1> When IICCn.WTIMn bit = 0 IICCn.
PAGE 847
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H (2) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) <1> When WTIMn bit = 0 ST AD6 to AD0 R/W ACK D7 to D0 S1 STTn bit = 1 SPTn bit = 1 ↓ ↓ ACK S2 ST AD6 to AD0 R/W ACK S3 D7 to D0 S4 ACK S5 SP S6 Δ7 S1: IICSn register = 1000X110B S2: IICSn register = 1000X000B (WTIMn bit = 1) S3: IICSn register = 1000XX00B (WTIMn bit = 0) S4: IICSn register = 1000X110B (WTIMn bit = 0) S5: IICSn register = 1000X000B (WTIMn bit = 1) S6: IICS
PAGE 848
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H (3) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) <1> When WTIMn bit = 0 SPTn bit = 1 ↓ ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK D7 to D0 S2 ACK S3 SP S4 Δ5 S1: IICSn register = 1010X110B S2: IICSn register = 1010X000B S3: IICSn register = 1010X000B (WTIMn bit = 1) S4: IICSn register = 1010XX00B Δ 5: IICSn register = 00000001B Remarks 1. S: Always generated Δ: Generated only when SPIEn bit = 1 X: don’t care 2.
PAGE 849
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H 19.7.2 Slave device operation (when receiving slave address data (address match)) (1) Start ~ Address ~ Data ~ Data ~ Stop <1> When IICCn.WTIMn bit = 0 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK D7 to D0 S2 ACK SP Δ4 S3 S1: IICSn register = 0001X110B S2: IICSn register = 0001X000B S3: IICSn register = 0001X000B Δ 4: IICSn register = 00000001B Remarks 1. S: Always generated Δ: Generated only when IICCn.SPIEn bit = 1 X: don’t care 2.
PAGE 850
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H (2) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address match) ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK ST AD6 to AD0 R/W ACK S2 D7 to D0 S3 ACK SP Δ5 S4 S1: IICSn register = 0001X110B S2: IICSn register = 0001X000B S3: IICSn register = 0001X110B S4: IICSn register = 0001X000B Δ 5: IICSn register = 00000001B Remarks 1. S: Always generated Δ: Generated only when SPIEn bit = 1 X: don’t care 2.
PAGE 851
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H (3) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, extension code reception) ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK ST AD6 to AD0 R/W S2 ACK D7 to D0 S3 ACK SP Δ5 S4 S1: IICSn register = 0001X110B S2: IICSn register = 0001X000B S3: IICSn register = 0010X010B S4: IICSn register = 0010X000B Δ 5: IICSn register = 00000001B Remarks 1.
PAGE 852
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H (4) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address mismatch (= not extension code)) ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK ST AD6 to AD0 R/W ACK S2 D7 to D0 ACK SP Δ4 S3 S1: IICSn register = 0001X110B S2: IICSn register = 0001X000B S3: IICSn register = 00000X10B Δ 4: IICSn register = 00000001B Remarks 1. S: Always generated Δ: Generated only when SPIEn bit = 1 X: don’t care 2.
PAGE 853
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H 19.7.3 Slave device operation (when receiving extension code) (1) Start ~ Code ~ Data ~ Data ~ Stop <1> When IICCn.WTIMn bit = 0 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK D7 to D0 S2 ACK SP Δ4 S3 S1: IICSn register = 0010X010B S2: IICSn register = 0010X000B S3: IICSn register = 0010X000B Δ 4: IICSn register = 00000001B Remarks 1. S: Always generated Δ: Generated only when IICCn.SPIEn bit = 1 X: don’t care 2.
PAGE 854
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H (2) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address match) ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK ST AD6 to AD0 R/W ACK S2 D7 to D0 S3 ACK SP Δ5 S4 S1: IICSn register = 0010X010B S2: IICSn register = 0010X000B S3: IICSn register = 0001X110B S4: IICSn register = 0001X000B Δ 5: IICSn register = 00000001B Remarks 1. S: Always generated Δ: Generated only when SPIEn bit = 1 X: don’t care 2.
PAGE 855
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H (3) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, extension code reception) ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK ST AD6 to AD0 R/W S2 ACK D7 to D0 S3 ACK SP Δ5 S4 S1: IICSn register = 0010X010B S2: IICSn register = 0010X000B S3: IICSn register = 0010X010B S4: IICSn register = 0010X000B Δ 5: IICSn register = 00000001B Remarks 1.
PAGE 856
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H (4) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address mismatch (= not extension code)) ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK ST AD6 to AD0 R/W ACK S2 D7 to D0 ACK SP Δ4 S3 S1: IICSn register = 0010X010B S2: IICSn register = 0010X000B S3: IICSn register = 00000X10B Δ 4: IICSn register = 00000001B Remarks 1. S: Always generated Δ: Generated only when SPIEn bit = 1 X: don’t care 2.
PAGE 857
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H 19.7.4 Operation without communication (1) Start ~ Code ~ Data ~ Data ~ Stop ST AD6 to AD0 R/W ACK D7 to D0 ACK D7 to D0 ACK SP Δ1 Δ 1: IICSn register = 00000001B Remarks 1. Δ: Generated only when SPIEn bit = 1 2. n = 0 to 2 19.7.5 Arbitration loss operation (operation as slave after arbitration loss) (1) When arbitration loss occurs during transmission of slave address data <1> When IICCn.
PAGE 858
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H (2) When arbitration loss occurs during transmission of extension code <1> When WTIMn bit = 0 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK D7 to D0 S2 ACK SP Δ4 S3 S1: IICSn register = 0110X010B (Example: When ALDn bit is read during interrupt servicing) S2: IICSn register = 0010X000B S3: IICSn register = 0010X000B Δ 4: IICSn register = 00000001B Remarks 1. S: Always generated Δ: Generated only when SPIEn bit = 1 X: don’t care 2.
PAGE 859
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H 19.7.6 Operation when arbitration loss occurs (no communication after arbitration loss) (1) When arbitration loss occurs during transmission of slave address data ST AD6 to AD0 R/W ACK D7 to D0 ACK D7 to D0 ACK SP Δ2 S1 S1: IICSn register = 01000110B (Example: When IICSn.ALDn bit is read during interrupt servicing) Δ 2: IICSn register = 00000001B Remarks 1. S: Always generated Δ: Generated only when IICCn.SPIEn bit = 1 2.
PAGE 860
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H (3) When arbitration loss occurs during data transfer <1> When IICCn.WTIMn bit = 0 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK D7 to D0 ACK SP Δ3 S2 S1: IICSn register = 10001110B S2: IICSn register = 01000000B (Example: When ALDn bit is read during interrupt servicing) Δ 3: IICSn register = 00000001B Remarks 1. S: Always generated Δ: Generated only when SPIEn bit = 1 2.
PAGE 861
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H (4) When arbitration loss occurs due to restart condition during data transfer <1> Not extension code (Example: Address mismatch) ST AD6 to AD0 R/W ACK D7 to Dn ST AD6 to AD0 R/W ACK S1 D7 to D0 ACK SP Δ3 S2 S1: IICSn register = 1000X110B S2: IICSn register = 01000110B (Example: When ALDn bit is read during interrupt servicing) Δ 3: IICSn register = 00000001B Remarks 1. S: Always generated Δ: Generated only when SPIEn bit = 1 X: don’t care 2.
PAGE 862
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H (5) When arbitration loss occurs due to stop condition during data transfer ST AD6 to AD0 R/W ACK D7 to Dn S1 SP Δ2 S1: IICSn register = 1000X110B Δ 2: IICSn register = 01000001B Remarks 1. S: Always generated Δ: Generated only when SPIEn bit = 1 X: don’t care 2. Dn = D6 to D0 n = 0 to 2 R01UH0042EJ0500 Rev.5.
PAGE 863
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H (6) When arbitration loss occurs due to low level of SDA0n pin when attempting to generate a restart condition <1> When WTIMn bit = 0 IICCn.
PAGE 864
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H (7) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition <1> When WTIMn bit = 0 STTn bit = 1 ↓ ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK S2 SP Δ4 S3 S1: IICSn register = 1000X110B S2: IICSn register = 1000X000B (WTIMn bit = 1) S3: IICSn register = 1000XX00B Δ 4: IICSn register = 01000001B Remarks 1. S: Always generated Δ: Generated only when SPIEn bit = 1 X: don’t care 2.
PAGE 865
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H (8) When arbitration loss occurs due to low level of SDA0n pin when attempting to generate a stop condition <1> When WTIMn bit = 0 IICCn.
PAGE 866
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H 19.8 Interrupt Request Signal (INTIICn) Generation Timing and Wait Control The setting of the IICCn.WTIMn bit determines the timing by which the INTIICn register is generated and the corresponding wait control, as shown below (n = 0 to 2). Table 19-3. INTIICn Generation Timing and Wait Control WTIMn Bit During Slave Device Operation Address 0 9 Notes 1, 2 1 9 Notes 1, 2 Notes 1.
PAGE 867
V850ES/JG3-H, V850ES/JH3-H CHAPTER 19 I2C BUS (4) Wait cancellation method The four wait cancellation methods are as follows. • By setting the IICCn.WRELn bit to 1 • By writing to the IICn register • By start condition setting (IICCn.STTn bit = 1)Note • By stop condition setting (IICCn.SPTn bit = 1)Note Note Master only When an 8-clock wait has been selected (WTIMn bit = 0), whether or not ACK has been generated must be determined prior to wait cancellation.
PAGE 868
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H 19.9 Address Match Detection Method In I2C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. Address match detection is performed automatically by hardware. The INTIICn signal occurs when a local address has been set to the SVAn register and when the address set to the SVAn register matches the slave address sent by the master device, or when an extension code has been received (n = 0 to 2). 19.
PAGE 869
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H 19.12 Arbitration When several master devices simultaneously generate a start condition (when the IICCn.STTn bit is set to 1 before the IICSn.STDn bit is set to 1), communication between the master devices is performed while the number of clocks is adjusted until the data differs. This kind of operation is called arbitration (n = 0 to 2). When one of the master devices loses in arbitration, an arbitration loss flag (IICSn.
PAGE 870
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H Table 19-5.
PAGE 871
V850ES/JG3-H, V850ES/JH3-H CHAPTER 19 I2C BUS 19.14 Communication Reservation 19.14.1 When communication reservation function is enabled (IICFn.IICRSVn bit = 0) To start master device communications when not currently using the bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. There are two modes in which the bus is not used.
PAGE 872
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H Table 19-6.
PAGE 873
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H Figure 19-15. Communication Reservation Timing Program processing Hardware processing SCL0n 1 2 3 4 STTn =1 Write to IICn Set SPDn and INTIICn Communication reservation 5 6 7 8 9 Set STDn 1 2 3 4 5 6 SDA0n Generated by master with bus access Remark n = 0 to 2 STTn: Bit of IICCn register STDn: Bit of IICSn register SPDn: Bit of IICSn register Communication reservations are accepted via the following timing. After the IICSn.
PAGE 874
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H The communication reservation flowchart is illustrated below. Figure 19-17. Communication Reservation Flowchart DI SET1 STTn Define communication reservation Wait Sets STTn bit (communication reservation). Defines that communication reservation is in effect (defines and sets user flag to any RAM). Secures wait period set by software (see Table 19-6).
PAGE 875
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H 19.14.2 When communication reservation function is disabled (IICFn.IICRSVn bit = 1) When the IICCn.STTn bit is set when the bus is not being used for communication during bus communication, this request is rejected and a start condition is not generated. There are two modes in which the bus is not used.
PAGE 876
V850ES/JG3-H, V850ES/JH3-H CHAPTER 19 I2C BUS 19.15 Cautions (1) When IICFn.STCENn bit = 0 Immediately after the I2C0n operation is enabled, the bus communication status (IICFn.IICBSYn bit = 1) is recognized regardless of the actual bus status. To execute master communication in the status where a stop condition has not been detected, generate a stop condition and then release the bus before starting the master communication. Use the following sequence for generating a stop condition.
PAGE 877
V850ES/JG3-H, V850ES/JH3-H CHAPTER 19 I2C BUS 19.16 Communication Operations The following shows three operation procedures together with flowcharts. (1) Master operation in single master system The flowchart when using the V850ES/JG3-H and V850ES/JH3-H as the master in a single master system is shown below. This flowchart is broadly divided into initial settings and communication processing. Execute the initial settings at startup.
PAGE 878
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H 19.16.1 Master operation in single master system Figure 19-18. Master Operation in Single Master System START Initialize I2C busNote Set ports Initial settings IICXn ← 0XH IICCLn ← XXH OCKSm ← XXH Refer to Table 4-20 Settings When Port Pins Are Used for Alternate Functions to set the I2C mode before this function is used.
PAGE 879
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H 19.16.2 Master operation in multimaster system Figure 19-19. Master Operation in Multimaster System (1/3) START Refer to Table 4-20 Settings When Port Pins Are Used for Alternate Functions to set the I2C mode before this function is used.
PAGE 880
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H Figure 19-19.
PAGE 881
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H Figure 19-19.
PAGE 882
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H 19.16.3 Slave operation The following shows the processing procedure of slave operation. Basically, the operation of the slave device is event-driven. Therefore, processing by an INTIICn interrupt (processing requiring a significant change of the operation status, such as stop condition detection during communication) is necessary. The following description assumes that data communication does not support extension codes.
PAGE 883
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H For reception, the required number of data is received and ACK is not returned for the next data immediately after transfer is complete. After that, the master device generates the stop condition or restart condition. This causes exit from communications. Figure 19-21. Slave Operation Flowchart (1) START Refer to Table 4-20 Settings When Port Pins Are Used for Alternate Functions to set the I2C mode before this function is used.
PAGE 884
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H The following shows an example of the processing of the slave device by an INTIICn interrupt (it is assumed that no extension codes are used here). During INTIICn interrupt servicing, the status is confirmed and the following steps are executed. <1> When a stop condition is detected, communication is terminated. <2> When a start condition is detected, the address is confirmed. If the address does not match, communication is terminated.
PAGE 885
V850ES/JG3-H, V850ES/JH3-H CHAPTER 19 I2C BUS 19.17 Timing of Data Communication When using I2C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the IICSn.TRCn bit, which specifies the data transfer direction, and then starts serial communication with the slave device.
PAGE 886
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H Figure 19-23.
PAGE 887
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H Figure 19-23.
PAGE 888
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H Figure 19-23.
PAGE 889
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H Figure 19-24.
PAGE 890
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H Figure 19-24.
PAGE 891
CHAPTER 19 I2C BUS V850ES/JG3-H, V850ES/JH3-H Figure 19-24.
PAGE 892
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER CHAPTER 20 CAN CONTROLLER Caution 1. The CAN controller is allocated in the programmable peripheral I/O area. Before using the CAN controller, enable use of the programmable peripheral I/O area by using the BPC register. For details, refer to 3.4.7 Programmable peripheral I/O registers. 2. When using the CAN controller, make sure that fXX = 32 to 48 MHz. 20.
PAGE 893
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER 20.1.2 Overview of functions Table 20-1 presents an overview of the CAN controller functions. Table 20-1.
PAGE 894
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER 20.1.3 Configuration The CAN controller is composed of the following four blocks. (1) Internal bus interface This functional block provides an internal bus interface and means of transmitting and receiving signals between the CAN module and the host CPU. (2) MCM (Memory Control Module) This functional block controls access to the CAN protocol layer and to the CAN RAM within the CAN module.
PAGE 895
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER 20.2 CAN Protocol CAN (Controller Area Network) is a high-speed multiplex communication protocol for real-time communication in automotive applications (class C). CAN is prescribed by ISO 11898. For details, refer to the ISO 11898 specifications. The CAN specification is generally divided into two layers: a physical layer and a data link layer. In turn, the data link layer includes logical link and medium access control.
PAGE 896
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER 20.2.2 Frame types The following four types of frames are used in the CAN protocol. Table 20-2. Frame Types Frame Type Description Data frame Frame used to transmit data Remote frame Frame used to request a data frame Error frame Frame used to report error detection Overload frame Frame used to delay the next data frame or remote frame (1) Bus value The bus values are divided into dominant and recessive.
PAGE 897
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER (2) Remote frame A remote frame is composed of six fields. Figure 20-4. Remote Frame Remote frame R D <1> <2> <3> <5> <6> <7> <8> Interframe space End of frame (EOF) ACK field CRC field Control field Arbitration field Start of frame (SOF) Remarks 1. The data field is not transferred even if the control field’s data length code is not “0000B”. 2.
PAGE 898
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER <2> Arbitration field The arbitration field is used to set the priority, data frame/remote frame, and frame format. Figure 20-6. Arbitration Field (in Standard Format Mode) Arbitration field (Control field) R D Identifier RTR IDE (r1) ID28 . . . . . . . . . . . . . . . . . . . . ID18 (11 bits) (1 bit) r0 (1 bit) Cautions 1. ID28 to ID18 are identifiers. 2. An identifier is transmitted MSB first.
PAGE 899
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER <3> Control field The control field sets “DLC” as the number of data bytes in the data field (DLC = 0 to 8). Figure 20-8. Control Field (Arbitration field) Control field (Data field) R D RTR Remark r1 (IDE) r0 DLC3 DLC2 DLC1 DLC0 D: Dominant = 0 R: Recessive = 1 In a standard format frame, the control field’s IDE bit is the same as the r1 bit. Table 20-5.
PAGE 900
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER <4> Data field The data field contains the amount of data (byte units) set by the control field. Up to 8 units of data can be set. Figure 20-9. Data Field (Control field) Data field (CRC field) R D MSB Remark Data 0 (8 bits) → MSB LSB Data 7 (8 bits) → LSB D: Dominant = 0 R: Recessive = 1 <5> CRC field The CRC field is a 16-bit field that is used to check for errors in transmit data. Figure 20-10.
PAGE 901
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER <6> ACK field The ACK field is used to acknowledge normal reception. Figure 20-11. ACK Field (CRC field) ACK field (End of frame) R D ACK slot (1 bit) Remark ACK delimiter (1 bit) D: Dominant = 0 R: Recessive = 1 • If no CRC error is detected, the receiving node sets the ACK slot to the dominant level. • The transmitting node outputs two recessive-level bits.
PAGE 902
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER <8> Interframe space The interframe space is inserted after a data frame, remote frame, error frame, or overload frame to separate one frame from the next. • The bus state differs depending on the error status. (a) Error active node The interframe space consists of a 3-bit intermission field and a bus idle field. Figure 20-13.
PAGE 903
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER • Operation in error status Table 20-6. Operation in Error Status Error Status Operation Error active A node in this status can transmit immediately after a 3-bit intermission. Error passive A node in this status can transmit 8 bits after the intermission. R01UH0042EJ0500 Rev.5.
PAGE 904
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER 20.2.4 Error frame An error frame is output by a node that has detected an error. Figure 20-15. Error Frame Error frame R D (<4>) <1> <2> <3> 6 bits 0 to 6 bits 8 bits (<5>) Interframe space or overload frame Error delimiter Error flag 2 Error flag 1 Error bit Remark D: Dominant = 0 R: Recessive = 1 Table 20-7. Definition of Error Frame Fields No.
PAGE 905
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER 20.2.5 Overload frame An overload frame is transmitted under the following conditions.
PAGE 906
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER 20.3 Functions 20.3.1 Determining bus priority (1) When a node starts transmission: • During bus idle, the node that output data first transmits the data.
PAGE 907
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER 20.3.5 CAN sleep mode/CAN stop mode function The CAN sleep mode/CAN stop mode function puts the CAN controller in waiting mode to achieve low power consumption. The controller is woken up from the CAN sleep mode by bus operation but it is not woken up from the CAN stop mode by bus operation (the CAN stop mode is controlled by CPU access). 20.3.6 Error control function (1) Error types Table 20-11.
PAGE 908
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER (4) Error state (a) Types of error states The following three types of error states are defined by the CAN specification. • Error active • Error passive • Bus-off These types of error states are classified by the values of the C0ERC.TEC7 to C0ERC.TEC0 bits (transmission error counter bits) and the C0ERC.REC6 to C0ERC.REC0 bits (reception error counter bits) as shown in Table 20-13. The present error state is indicated by the C0INFO register.
PAGE 909
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Table 20-13.
PAGE 910
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER (b) Error counter The error counter counts up when an error has occurred, and counts down upon successful transmission and reception. The error counter counts up immediately after error detection. Table 20-14.
PAGE 911
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER (5) Recovery from bus-off state When the CAN module is in the bus-off state, the transmission pins (CTXD0) cut off from the CAN bus always output the recessive level. The CAN module recovers from the bus-off state in the following bus-off recovery sequence.
PAGE 912
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Figure 20-17.
PAGE 913
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER (6) Initializing CAN module error counter register (C0ERC) in initialization mode If it is necessary to initialize the C0ERC and C0INFO registers for debugging or evaluating a program, they can be initialized to the default value by setting the C0CTRL.CCERC bit in the initialization mode. When initialization has been completed, the CCERC bit is automatically cleared to 0. Cautions 1. This function is enabled only in the initialization mode.
PAGE 914
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER 20.3.7 Baud rate control function (1) Prescaler The CAN controller has a prescaler that divides the clock (fCAN) supplied to CAN. This prescaler generates a CAN protocol layer base clock (fTQ) that is the CAN module system clock (fCANMOD) divided by 1 to 256 (see 20.6 (12) CAN0 module bit rate prescaler register (C0BRP)). (2) Data bit time (8 to 25 time quanta) One data bit time is defined as shown in Figure 20-18.
PAGE 915
V850ES/JG3-H, V850ES/JH3-H Remark CHAPTER 20 CAN CONTROLLER The CAN protocol specification defines the segments constituting the data bit time as shown in Figure 20-19. Figure 20-19.
PAGE 916
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER (3) Synchronizing data bit • The receiving node establishes synchronization by a level change on the bus because it does not have a sync signal. • The transmitting node transmits data in synchronization with the bit timing of the transmitting node. (a) Hardware synchronization This synchronization is established when the receiving node detects the start of frame in the interframe space.
PAGE 917
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER (b) Resynchronization Synchronization is established again if a level change is detected on the bus during reception (only if a recessive level was sampled previously). • The phase error of the edge is given by the relative position of the detected edge and sync segment.
PAGE 918
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER 20.4 Connection with Target System The microcontroller with on-chip CAN controller has to be connected to the CAN bus using an external transceiver. Figure 20-22. Connection to CAN Bus Microcontroller with on-chip CAN controller R01UH0042EJ0500 Rev.5.
PAGE 919
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER 20.5 Internal Registers of CAN Controller 20.5.1 CAN controller configuration Table 20-15.
PAGE 920
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER 20.5.2 Register access type Table 20-16.
PAGE 921
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Table 20-16.
PAGE 922
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Table 20-16.
PAGE 923
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Table 20-16.
PAGE 924
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Table 20-16.
PAGE 925
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Table 20-16.
PAGE 926
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Table 20-16.
PAGE 927
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Table 20-16.
PAGE 928
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Table 20-16.
PAGE 929
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Table 20-16.
PAGE 930
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Table 20-16.
PAGE 931
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Table 20-16.
PAGE 932
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Table 20-16.
PAGE 933
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Table 20-16.
PAGE 934
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Table 20-16.
PAGE 935
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Table 20-16.
PAGE 936
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Table 20-16.
PAGE 937
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER 20.5.3 Register bit configuration Table 20-17.
PAGE 938
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Table 20-18.
PAGE 939
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Table 20-18.
PAGE 940
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Table 20-19.
PAGE 941
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER 20.6 Registers Caution Accessing the CAN controller registers is prohibited in the following statuses. For details, refer to 3.4.9 (2) Accessing specific on-chip peripheral I/O registers. • When the CPU operates with the subclock and the main clock oscillation is stopped • When the CPU operates with the internal oscillation clock Remark m = 00 to 31 R01UH0042EJ0500 Rev.5.
PAGE 942
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER (1) CAN0 global control register (C0GMCTRL) The C0GMCTRL register is used to control the operation of the CAN module.
PAGE 943
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER (2/2) EFSD Bit enabling forced shut down 0 Forced shut down by GOM bit = 0 disabled. 1 Forced shut down by GOM bit = 0 enabled. Caution To request forced shut down, clear the GOM bit to 0 immediately after the EFSD bit has been set to 1.
PAGE 944
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER (2) CAN0 global clock selection register (C0GMCS) The C0GMCS register is used to select the CAN module system clock.
PAGE 945
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER (3) CAN0 global automatic block transmission control register (C0GMABT) The C0GMABT register is used to control the automatic block transmission (ABT) operation.
PAGE 946
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER (2/2) (b) Write Set ABTCLR Automatic block transmission engine clear request bit 0 The automatic block transmission engine is in idle status or under operation. 1 Request to clear the automatic block transmission engine. After the automatic block transmission engine has been cleared, automatic block transmission is started from message buffer 0 by setting the ABTTRG bit to 1.
PAGE 947
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER (4) CAN0 global automatic block transmission delay register (C0GMABTD) The C0GMABTD register is used to set the interval at which the data of the message buffer assigned to ABT is to be transmitted in the normal operation mode with ABT.
PAGE 948
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER (5) CAN0 module mask control register (C0MASKaL, C0MASKaH) (a = 1, 2, 3, or 4) The C0MASKaL and C0MASKaH registers are used to extend the number of receivable messages in the same message buffer by masking part of the identifier (ID) of a message and invalidating the ID comparison of the masked part.
PAGE 949
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER (2/2) • CAN0 module mask 3 register (C0MASK3L, C0MASK3H) After reset: Undefined C0MASK3L Address: C0MASK3L 03FEC048H, C0MASK3H 03FEC04AH 15 14 13 12 11 10 9 8 CMID15 CMID14 CMID13 CMID12 CMID11 CMID10 CMID9 CMID8 7 6 5 4 3 2 1 0 CMID7 CMID6 CMID5 CMID4 CMID3 CMID2 CMID1 CMID0 15 14 13 12 11 10 9 8 0 0 0 CMID28 CMID27 CMID26 CMID25 CMID24 7 6 5 4 3 2 1 0 CMID23 CMID22 CMID21 CMID20 CMID19 C
PAGE 950
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER (6) CAN0 module control register (C0CTRL) The C0CTRL register is used to control the operation mode of the CAN module.
PAGE 951
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER (2/4) CCERC Error counter clear bit 0 The C0ERC and C0INFO registers are not cleared in the initialization mode. 1 The C0ERC and C0INFO registers are cleared in the initialization mode. Remarks 1. The CCERC bit is used to clear the C0ERC and C0INFO registers for re-initialization or forced recovery from the bus-off status. This bit can be set to 1 only in the initialization mode. 2.
PAGE 952
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER (3/4) PSMODE1 PSMODE0 Power save mode 0 0 No power save mode is selected. 0 1 CAN sleep mode 1 0 Setting prohibited 1 1 CAN stop mode Cautions 1. Transition to and from the CAN stop mode must be made via CAN sleep mode. A request for direct transition to and from the CAN stop mode is ignored. 2. After releasing the power save mode, the C0GMCTRL.MBON flag must be checked before accessing the message buffer again. 3.
PAGE 953
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER (4/4) Set PSMODE0 Clear PSMODE0 0 1 PSMODE0 bit is cleared to 0. 1 0 PSMODE bit is set to 1. Other than above Setting of PSMODE0 bit PSMODE0 bit is not changed. Set PSMODE1 Clear PSMODE1 0 1 PSMODE1 bit is cleared to 0. 1 0 PSMODE1 bit is set to 1. Other than above Setting of PSMODE1 bit PSMODE1 bit is not changed. Set OPMODE0 Clear OPMODE0 0 1 OPMODE0 bit is cleared to 0. 1 0 OPMODE0 bit is set to 1.
PAGE 954
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER (7) CAN0 module last error information register (C0LEC) The C0LEC register provides the error information of the CAN protocol. After reset: 00H C0LEC R/W Address: 03FEC052H 7 6 5 4 3 2 1 0 0 0 0 0 0 LEC2 LEC1 LEC0 LEC2 LEC1 LEC0 Last CAN protocol error information 0 0 0 No error 0 0 1 Stuff error 0 1 0 Form error 0 1 1 ACK error 1 0 0 Bit error.
PAGE 955
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER (8) CAN0 module information register (C0INFO) The C0INFO register indicates the status of the CAN module. After reset: 00H C0INFO R Address: 03FEC053H 7 6 5 4 3 2 1 0 0 0 0 BOFF TECS1 TECS0 RECS1 RECS0 BOFF Bus-off status bit 0 Not bus-off status (transmit error counter ≤ 255). (The value of the transmit counter is less than 256.) 1 Bus-off status (transmit error counter > 255).
PAGE 956
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER (9) CAN0 module error counter register (C0ERC) The C0ERC register indicates the count value of the transmission/reception error counter.
PAGE 957
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER (10) CAN0 module interrupt enable register (C0IE) The C0IE register is used to enable or disable the interrupts of the CAN module.
PAGE 958
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER (2/2) (b) Write Set CIE5 Clear CIE5 0 1 CIE5 bit is cleared to 0. 1 0 CIE5 bit is set to 1. Other than above Setting of CIE5 bit CIE5 bit is not changed. Set CIE4 Clear CIE4 0 1 CIE4 bit is cleared to 0. 1 0 CIE4 bit is set to 1. Other than above Setting of CIE4 bit CIE4 bit is not changed. Set CIE3 Clear CIE3 0 1 CIE3 bit is cleared to 0. 1 0 CIE3 bit is set to 1.
PAGE 959
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER (11) CAN0 module interrupt status register (C0INTS) The C0INTS register indicates the interrupt status of the CAN module.
PAGE 960
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER (12) CAN0 module bit rate prescaler register (C0BRP) The C0BRP register is used to select the CAN protocol layer base clock (fTQ). The communication baud rate is set to the C0BTR register.
PAGE 961
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER (13) CAN0 module bit rate register (C0BTR) The C0BTR register is used to control the data bit time of the communication baud rate. Figure 20-24. Data Bit Time Data bit time (DBT) Sync segment Prop segment Phase segment 1 Time segment 1 (TSEG1) R01UH0042EJ0500 Rev.5.
PAGE 962
V850ES/JG3-H, V850ES/JH3-H After reset: 370FH C0BTR R/W CHAPTER 20 CAN CONTROLLER Address: 03FEC05CH 15 14 13 12 11 10 9 8 0 0 SJW1 SJW0 0 TSEG22 TSEG21 TSEG20 7 6 5 4 3 2 1 0 0 0 0 0 TSEG13 TSEG12 TSEG11 TSEG10 SJW1 SJW0 0 0 1TQ 0 1 2TQ 1 0 3TQ 1 1 4TQ (default value) TSEG22 TSEG21 TSEG20 0 0 0 1TQ 0 0 1 2TQ 0 1 0 3TQ 0 1 1 4TQ 1 0 0 5TQ 1 0 1 6TQ 1 1 0 7TQ 1 1 1 8TQ (default value) TSEG13 TSEG12 TSEG11 TSEG10 0 0
PAGE 963
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER (14) CAN0 module last in-pointer register (C0LIPT) The C0LIPT register indicates the number of the message buffer in which a data frame or a remote frame was last stored.
PAGE 964
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER (15) CAN0 module receive history list register (C0RGPT) The C0RGPT register is used to read the receive history list.
PAGE 965
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER (2/2) (b) Write Clear ROVF Setting of ROVF bit 0 ROVF bit is not changed. 1 ROVF bit is cleared to 0. (16) CAN0 module last out-pointer register (C0LOPT) The C0LOPT register indicates the number of the message buffer to which a data frame or a remote frame was transmitted last.
PAGE 966
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER (17) CAN0 module transmit history list register (C0TGPT) The C0TGPT register is used to read the transmit history list.
PAGE 967
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER (2/2) (b) Write Clear TOVF Setting of TOVF bit 0 TOVF bit is not changed. 1 TOVF bit is cleared to 0. (18) CAN0 module time stamp register (C0TS) The C0TS register is used to control the time stamp function.
PAGE 968
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER (2/2) (a) Read TSLOCK Time stamp lock function enable bit Time stamp lock function stopped. 0 The TSOUT signal toggles each time the selected time stamp capture event occurs. Time stamp lock function enabled. 1 The TSOUT signal toggled each time the selected time stamp capture event occurred. However, the TSOUT output signal is locked when a data frame has been correctly received to message buffer 0 Note Note .
PAGE 969
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER (19) CAN0 message data byte register (C0MDATAxm, C0MDATAym) (x = 0 to 7, y = 01, 23, 45, 67) The C0MDATAxm register is used to store the data of a transmit/receive message, and can be accessed in 8-bit unit. The C0MDATAxm register can be accessed in 16-bit units by the C0MDATAym register. (1/2) After reset: Undefined C0MDATA01m C0MDATA0m C0MDATA1m C0MDATA23m C0MDATA2m C0MDATA3m R/W Address: See Table 20-16.
PAGE 970
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER (2/2) C0MDATA45m C0MDATA4m C0MDATA5m C0MDATA67m C0MDATA6m C0MDATA7m 15 14 13 12 11 10 9 8 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MDATA4 MDATA4 MDATA4 MDATA4 MDATA4 MDATA4 MDATA4 MDATA4 7 6 5 4 3 2 1 0 7 6 5 4 3 2
PAGE 971
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER (20) CAN0 message data length register m (C0MDLCm) The C0MDLCm register is used to set the number of bytes of the data field of a message buffer. After reset: 0000xxxxB C0MDLCm R/W Address: See Table 20-16.
PAGE 972
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER (21) CAN0 message configuration register m (C0MCONFm) The C0MCONFm register is used to specify the type of the message buffer and to set a mask. (1/2) After reset: Undefined C0MCONFm R/W Address: See Table 20-16. 7 6 5 4 3 2 1 0 OWS RTR MT2 MT1 MT0 0 0 MA0 OWS Overwrite control bit Note The message buffer 0 that has already received a data frame is not overwritten by a newly received data frame.
PAGE 973
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER (2/2) MA0 Message buffer assignment bit 0 Message buffer not used. 1 Message buffer used. Caution Be sure to set bits 2 and 1 to “0”. (22) CAN0 message ID register m (C0MIDLm, C0MIDHm) The C0MIDLm and C0MIDHm registers are used to set an identifier (ID). After reset: Undefined C0MIDLm C0MIDHm R/W Address: See Table 20-16.
PAGE 974
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER (23) CAN0 message control register m (C0MCTRLm) The C0MCTRLm register is used to control the operation of the message buffer. (1/3) After reset: 00x000000 R/W Address: See Table 20-16.
PAGE 975
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER (2/3) TRQ Message buffer transmission request bit 0 No message frame transmitting request that is pending or being transmitted is in the message buffer. 1 The message buffer is holding transmission of a message frame pending or is transmitting a message frame. Caution Do not set the TRQ bit and RDY bit to 1 at the same time. Be sure to set the RDY bit to 1 before setting the TRQ bit to 1.
PAGE 976
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER (3/3) Set TRQ Clear TRQ 0 1 TRQ bit is cleared to 0. 1 0 TRQ bit is set to 1. Other than above Setting of TRQ bit TRQ bit is not changed. Caution Even if the TRQ bit is set (1), transmission may not be immediately executed depending on the situation such as when a message is received from another node or when a message is transmitted from the message buffer. Transmission under execution is not terminated midway even if the TRQ bit is cleared.
PAGE 977
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER 20.7 Bit Set/Clear Function The CAN control registers include registers whose bits can be set or cleared via the CPU and via the CAN interface. An operation error occurs if the following registers are written directly. Do not write any values directly via bit manipulation, read/modify/write, or direct writing of target values.
PAGE 978
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Figure 20-26. Bit Status After Bit Setting/Clearing Operations 15 14 13 12 11 10 9 Set 7 Set 6 Set 5 Set 4 Set 3 Set 2 Set 1 Remark 8 7 6 5 4 3 2 1 0 Set 0 Clear 7 Clear 6 Clear 5 Clear 4 Clear 3 Clear 2 Clear 1 Clear 0 Set n Clear n Status of bit n after bit set/clear operation 0 0 No change 0 1 0 1 0 1 1 1 No change n = 0 to 7 R01UH0042EJ0500 Rev.5.
PAGE 979
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER 20.8 CAN Controller Initialization 20.8.1 Initialization of CAN module Before CAN module operation is enabled, the CAN module system clock needs to be determined by setting the C0GMCS.CCP0 to C0GMCS.CCP3 bits by software. Do not change the setting of the CAN module system clock after CAN module operation is enabled. The CAN module is enabled by setting the C0GMCTRL.GOM bit. For the procedure of initializing the CAN module, see 20.
PAGE 980
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Figure 20-27. Setting Transmission Request (TRQ) to Transmit Message Buffer After Redefinition Redefinition completed Execute transmission? No Yes Wait for 1 bit of CAN data. Set TRQ bit Set TRQ bit = 1 Clear TRQ bit = 0 END Cautions 1. When a message is received, reception filtering is performed in accordance with the ID and mask set to each receive message buffer.
PAGE 981
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Figure 20-28. Transition to Operation Modes OPMODE[2:0] = 00H and CAN bus is busy. [Receive-only mode] OPMODE[2:0]=03H OPMODE[2:0] = 00H and CAN bus is busy. OPMODE[2:0] = 00H and CAN bus is busy. [Normal operation mode with ABT] OPMODE[2:0]=02H OPMODE[2:0] = 03H OPMODE[2:0] = 00H and interframe space OPMODE[2:0] = 00H and interframe space OPMODE[2:0] = 04H OPMODE[2:0] = 02H OPMODE[2:0] = 00H and CAN bus is busy.
PAGE 982
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER 20.9 Message Reception 20.9.1 Message reception All buffers satisfying the following conditions are searched in all the message buffer areas in all the operation modes in order to store newly receive messages. • Used as a message buffer (C0MCONFm.MA0 bit is set to 1.) • Set as a receive message buffer (C0MCONFm.MT2 to C0MCONFm.MT0 bits are set to 001B, 010B, 011B, 100B, or 101B.) • Ready for reception (C0MCTRLm.RDY bit is set to 1.
PAGE 983
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER 20.9.2 Reading reception data If it is necessary to consistently read data from the CAN message buffer by software, follow the recommended procedures shown in Figures 20-49 and 20-50. While receiving a message, the CAN module sets the C0MCTRLm.DN bit two times, at the beginning of the processing to store data in the message buffer and at the end of this storing processing. During this storing processing, the C0MCTRLm.
PAGE 984
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER 20.9.3 Receive history list function The receive history list (RHL) function records in the receive history list the number of the receive message buffer in which each data frame or remote frame was received and stored. The RHL consists of storage elements equivalent to up to 23 messages, the last in-message pointer (LIPT) with the corresponding C0LIPT register and the receive history list get pointer (RGPT) with the corresponding C0RGPT register.
PAGE 985
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER As long as the RHL contains 23 or less entries the sequence of occurrence is maintained. If more receptions occur without the RHL being read by the host processor, a complete sequence of receptions can not be recovered. Figure 20-30. Receive History List Receive history list (RHL) Receive history list (RHL) 23 22 : : : Last inmessage pointer (LIPT) 7 6 5 4 3 2 1 0 23 22 Event: - Message buffer 6, 9, 2, and 7 are read by host processor.
PAGE 986
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER 20.9.4 Mask function For some message buffers that are used for reception, whether one of four global reception masks is applied can be selected. Load resulting from comparing message identifiers is reduced by masking some bits, and, as a result, some different identifiers can be received in a buffer. By using the mask function, the identifier of a message received from the CAN bus can be compared with the identifier set to a message buffer in advance.
PAGE 987
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER <3> Mask setting for CAN module 1 (mask 1) (Example) (Using CAN1 address mask 1 registers L and H (C1MASK1L and C1MASK1H)) CMID28 CMID27 CMID26 CMID25 CMID24 CMID23 CMID22 CMID21 CMID20 CMID19 CMID18 1 0 0 0 0 1 0 1 1 1 1 CMID17 CMID16 CMID15 CMID14 CMID13 CMID12 CMID11 CMID10 CMID9 CMID8 CMID7 1 1 1 1 1 1 1 1 1 1 1 CMID6 CMID5 CMID4 CMID3 CMID2 CMID1 CMID0 1 1 1 1 1 1 1 1: Not compared (masked)
PAGE 988
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER 20.9.5 Multi buffer receive block function The multi buffer receive block (MBRB) function is used to store a block of data in two or more message buffers sequentially with no CPU interaction, by setting the same ID to two or more message buffers with the same message buffer type. These message buffers can be allocated in any area in the message buffer memory, and they are not necessarily to be allocated adjacent to each other.
PAGE 989
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER 20.9.6 Remote frame reception In all the operation modes, when a remote frame is received, the message buffer that is to store the remote frame is searched from all the message buffers satisfying the following conditions. • Used as a message buffer (C0MCONFm.MA0 bit set to 1.) • Set as a transmit message buffer (C0MCONFm.MT2 to C0MCONFm.MT0 bits set to 000B) • Ready for reception (C0MCTRLm.RDY bit set to 1.) • Set to transmit message (C0MCONFm.
PAGE 990
V850ES/JG3-H, V850ES/JH3-H 20.10 Message Transmission 20.10.1 Message transmission CHAPTER 20 CAN CONTROLLER In all the operation modes, if the C0MCTRLm.TRQ bit is set to 1 in a message buffer that satisfies the following conditions, the message buffer that is to transmit a message is searched. • Used as a message buffer (C0MCONFm.MA0 bit set to 1.) • Set as a transmit message buffer (C0MCONFm.MT2 to C0MCONFm.MT0 bits set to 000B.) • Ready for transmission (C0MCTRLm.RDY bit is set to 1.
PAGE 991
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER After the transmit message search, the transmit message with the highest priority of the transmit message buffers that have a pending transmission request (message buffers with the TRQ bit set to 1 in advance) is transmitted. If a new transmission request is set, the transmit message buffer with the new transmission request is compared with the transmit message buffer with a pending transmission request.
PAGE 992
V850ES/JG3-H, V850ES/JH3-H 20.10.2 CHAPTER 20 CAN CONTROLLER Transmit history list function The transmit history list (THL) function records in the transmit history list the number of the transmit message buffer in which each data frame or remote frame was received and stored.
PAGE 993
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Figure 20-32. Transmit History List Transmit history list (THL) Transmit history list (THL) Last outmessage pointer (LOPT) 7 6 5 4 3 2 1 0 Event: Message buffer Message buffer Message buffer Message buffer 7 2 9 6 - CPU confirms Tx completion of message buffer 6, 9, and 2. - Tx completion of message buffer 3, and 4.
PAGE 994
V850ES/JG3-H, V850ES/JH3-H 20.10.3 CHAPTER 20 CAN CONTROLLER Automatic block transmission (ABT) The automatic block transmission (ABT) function is used to transmit two or more data frames successively with no CPU interaction. The maximum number of transmit message buffers assigned to the ABT function is eight (message buffer numbers 0 to 7). By setting the C0CTRL.OPMODE2 to C0CTRL.
PAGE 995
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Cautions 1. To resume the normal operation mode with ABT from the message buffer 0, set the ABTCLR bit to 1 while the ABTTRG bit is cleared to 0. If the ABTCLR bit is set to 1 while the ABTTRG bit is set to 1, the subsequent operation is not guaranteed. 2.
PAGE 996
V850ES/JG3-H, V850ES/JH3-H 20.10.4 CHAPTER 20 CAN CONTROLLER Transmission abort process Remark m = 00 to 31 (1) Transmission abort process other than in normal operation mode with automatic block transmission (ABT) The user can clear the C0MCTRLm.TRQ bit to 0 to abort a transmission request. The TRQ bit will be cleared immediately if the abort was successful. Whether the transmission was successfully aborted or not can be checked using the C0CTRL.
PAGE 997
V850ES/JG3-H, V850ES/JH3-H 20.10.5 CHAPTER 20 CAN CONTROLLER Remote frame transmission Remote frames can be transmitted only from transmit message buffers. Set whether a data frame or remote frame is transmitted via the C0MCONFm.RTR bit. Setting (1) the RTR bit sets remote frame transmission. Remark m = 00 to 31 R01UH0042EJ0500 Rev.5.
PAGE 998
V850ES/JG3-H, V850ES/JH3-H 20.11 CHAPTER 20 CAN CONTROLLER Power Saving Modes 20.11.1 CAN sleep mode The CAN sleep mode can be used to set the CAN controller to standby mode in order to reduce power consumption. The CAN module can enter the CAN sleep mode from all operation modes. Release of the CAN sleep mode returns the CAN module to exactly the same operation mode from which the CAN sleep mode was entered.
PAGE 999
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER (2) Status in CAN sleep mode The CAN module is in one of the following states after it enters the CAN sleep mode. • The internal operating clock is stopped and the power consumption is minimized. • The function to detect the falling edge of the CAN reception pin (CRXD0) remains in effect to wake up the CAN module from the CAN bus.
PAGE 1000
V850ES/JG3-H, V850ES/JH3-H 20.11.2 CHAPTER 20 CAN CONTROLLER CAN stop mode The CAN stop mode can be used to set the CAN controller to standby mode to reduce power consumption. The CAN module can enter the CAN stop mode only from the CAN sleep mode. Release of the CAN stop mode puts the CAN module in the CAN sleep mode. The CAN stop mode can only be released (shifting to CAN sleep mode) by writing 01B to the C0CTRL.PSMODE1 and C0CTRL.PSMODE0 bits and not by a change in the CAN bus state.
PAGE 1001
V850ES/JG3-H, V850ES/JH3-H 20.11.3 CHAPTER 20 CAN CONTROLLER Example of using power saving modes In some application systems, it may be necessary to place the CPU in a power saving mode to reduce the power consumption. By using the power saving mode specific to the CAN module and the power saving mode specific to the CPU in combination, the CPU can be woken up from the power saving status by the CAN bus. Here is an example of using the power saving modes.
PAGE 1002
V850ES/JG3-H, V850ES/JH3-H 20.12 CHAPTER 20 CAN CONTROLLER Interrupt Function The CAN module provides 6 different interrupt sources. The occurrence of these interrupt sources is stored in interrupt status registers. Four separate interrupt request signals are generated from the six interrupt sources. When an interrupt request signal that corresponds to two or more interrupt sources is generated, the interrupt sources can be identified by using an interrupt status register.
PAGE 1003
V850ES/JG3-H, V850ES/JH3-H 20.13 CHAPTER 20 CAN CONTROLLER Diagnosis Functions and Special Operational Modes The CAN module provides a receive-only mode, single-shot mode, and self-test mode to support CAN bus diagnosis functions or the operation of special CAN communication methods. 20.13.1 Receive-only mode The receive-only mode is used to monitor receive messages without causing any interference on the CAN bus and can be used for CAN bus analysis nodes.
PAGE 1004
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER In the receive-only mode, no message frames can be transmitted from the CAN module to the CAN bus. Transmit requests issued for message buffers defined as transmit message buffers are held pending. In the receive-only mode, the CAN transmission pin (CTXD0) in the CAN module is fixed to the recessive level.
PAGE 1005
V850ES/JG3-H, V850ES/JH3-H 20.13.3 CHAPTER 20 CAN CONTROLLER Self-test mode In the self-test mode, message frame transmission and message frame reception can be tested without connecting the CAN node to the CAN bus or without affecting the CAN bus. In the self-test mode, the CAN module is completely disconnected from the CAN bus, but transmission and reception are internally looped back. The CAN transmission pin (CTXD0) is fixed to the recessive level.
PAGE 1006
V850ES/JG3-H, V850ES/JH3-H 20.13.4 CHAPTER 20 CAN CONTROLLER Transmission/reception operation in each operation mode Table 20-21 shows the transmission/reception operation in each operation mode. Table 20-21.
PAGE 1007
V850ES/JG3-H, V850ES/JH3-H 20.14 CHAPTER 20 CAN CONTROLLER Time Stamp Function CAN is an asynchronous, serial protocol. All nodes connected to the CAN bus have a local, autonomous clock. As a consequence, the clocks of the nodes have no relation (i.e., the clocks are asynchronous and may even have different frequencies). In some applications, however, a common time base over the network (= global time base) is needed. In order to build up a global time base, a time stamp function is used.
PAGE 1008
V850ES/JG3-H, V850ES/JH3-H Caution CHAPTER 20 CAN CONTROLLER The time stamp function using the TSLOCK bit stops toggle of the TSOUT signal by receiving a data frame in message buffer 0. Therefore, message buffer 0 must be set as a receive message buffer. Since a receive message buffer cannot receive a remote frame, toggle of the TSOUT signal cannot be stopped by reception of a remote frame.
PAGE 1009
V850ES/JG3-H, V850ES/JH3-H 20.15 CHAPTER 20 CAN CONTROLLER Baud Rate Settings 20.15.1 Bit rate setting conditions Make sure that the settings are within the range of limit values for ensuring correct operation of the CAN controller, as follows.
PAGE 1010
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Table 20-22. Settable Bit Rate Combinations (1/3) Valid Bit Rate Setting C0BTR Register Setting Value Sampling Point (Unit: %) SYNC PROP PHASE PHASE TSEG13 to TSEG22 to SEGMENT SEGMENT SEGMENT1 SEGMENT2 TSEG10 TSEG20 25 1 8 8 8 1111 111 68.0 24 1 7 8 8 1110 111 66.7 24 1 9 7 7 1111 110 70.8 23 1 6 8 8 1101 111 65.2 23 1 8 7 7 1110 110 69.6 23 1 10 6 6 1111 101 73.
PAGE 1011
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Table 20-22. Settable Bit Rate Combinations (2/3) Valid Bit Rate Setting C0BTR Register Setting Value Sampling Point (Unit: %) SYNC PROP PHASE PHASE TSEG13 to TSEG22 to SEGMENT SEGMENT SEGMENT1 SEGMENT2 TSEG10 TSEG20 17 1 2 7 7 1000 110 58.8 17 1 4 6 6 1001 101 64.7 17 1 6 5 5 1010 100 70.6 17 1 8 4 4 1011 011 76.5 17 1 10 3 3 1100 010 82.4 17 1 12 2 2 1101 001 88.
PAGE 1012
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Table 20-22. Settable Bit Rate Combinations (3/3) Valid Bit Rate Setting C0BTR Register Setting Value Sampling Point (Unit: %) SYNC PROP PHASE PHASE TSEG13 to TSEG22 to SEGMENT SEGMENT SEGMENT1 SEGMENT2 TSEG10 TSEG20 11 1 2 4 4 0101 011 63.6 11 1 4 3 3 0110 010 72.7 11 1 6 2 2 0111 001 81.8 11 1 8 1 1 1000 000 90.9 10 1 1 4 4 0100 011 60.0 10 1 3 3 3 0101 010 70.
PAGE 1013
V850ES/JG3-H, V850ES/JH3-H 20.15.2 CHAPTER 20 CAN CONTROLLER Representative examples of baud rate settings Tables 20-23 and 20-24 show representative examples of baud rate settings. Table 20-23.
PAGE 1014
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Table 20-23. Representative Examples of Baud Rate Settings (fCANMOD = 8 MHz) (2/2) Set Baud Division C0BRP Rate Value Ratio of Register Set (Unit: kbps) C0BRP Value Register Valid Bit Rate Setting (Unit: kbps) C0BTR Register Setting Length of SYNC DBT SEGMENT PROP PHASE PHASE SEGMENT SEGMENT1 SEGMENT2 Sampling Point Value TSEG13 to TSEG22 to TSEG10 TSEG20 (Unit: %) 100 4 00000011 20 1 7 6 6 1100 101 70.
PAGE 1015
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Table 20-24. Representative Examples of Baud Rate Settings (fCANMOD = 16 MHz) (1/2) Set Baud Division C0BRP Rate Value Ratio of Register Set (Unit: kbps) C0BRP Value Register Valid Bit Rate Setting (Unit: kbps) C0BTR Register Setting Value Length of SYNC DBT SEGMENT PROP PHASE PHASE SEGMENT SEGMENT1 SEGMENT2 Sampling Point TSEG13 to TSEG22 to TSEG10 TSEG20 (Unit: %) 1000 1 00000000 16 1 1 7 7 0111 110 56.
PAGE 1016
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Table 20-24. Representative Examples of Baud Rate Settings (fCANMOD = 16 MHz) (2/2) Set Baud Division C0BRP Rate Value Ratio of Register Set (Unit: kbps) C0BRP Value 8 C0BTR Register Setting Value Length of SYNC DBT SEGMENT 00000111 20 1 9 5 Register 100 Valid Bit Rate Setting (Unit: kbps) PROP PHASE Sampling Point (Unit: %) TSEG13 to TSEG22 to TSEG10 TSEG20 5 1101 100 75.
PAGE 1017
V850ES/JG3-H, V850ES/JH3-H 20.16 CHAPTER 20 CAN CONTROLLER Operation of CAN Controller The processing procedure shown below is recommended to operate the CAN controller. Develop your program by referring to this recommended processing procedure. Remark m = 00 to 31 Figure 20-36. Initialization START Set C0GMCS register. Set C0GMCTRL register (set GOM bit = 1) Set C0BRP register, C0BTR register. Set C0IE register. Set C0MASK register. Initialize message buffers.
PAGE 1018
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Figure 20-37. Re-initialization START Clear OPMODE. INIT mode? No Yes Set C0BRP register, C0BTR register. Set C0IE register. Set C0MASK register. Initialize message buffers. C0ERC and C0INFO register clear? No Yes Set CCERC bit. Set CCERC bit = 1 Set C0CTRL register. (set OPMODE bit) END Caution After setting the CAN module to the initialization mode, avoid setting the module to another operation mode immediately after.
PAGE 1019
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Figure 20-38. Message Buffer Initialization START No RDY bit = 1? Yes Clear RDY bit. Set RDY bit = 0 Clear RDY bit = 1 No RDY bit = 0? Yes Set C0MCONFm register. Set C0MIDHm register, C0MIDLm register. Transmit message buffer? No Yes Set C0MDLCm register. Clear C0MDATAm register. Set C0MCTRLm register. Set RDY bit. Set RDY bit = 1 Clear RDY bit = 0 END Cautions 1. Before a message buffer is initialized, the RDY bit must be cleared. 2.
PAGE 1020
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Figure 20-39 shows the processing for a receive message buffer (C0MCONFm.MT2 to C0MCONFm.MT0 bits = 001B to 101B). Figure 20-39. Message Buffer Redefinition START Clear VALID bit. C0CTRLCLEAR_VALID =1 No RDY = 1? Yes Clear RDY bit. C0MCTRLm.SET_RDY = 0 C0MCTRLm.CLEAR_RDY = 1 RDY = 0? No Yes RSTAT = 0 or Note 1 VALID = 1? No Yes Wait for a period of 4 CAN data Note 2 bits . Set message buffers. Set RDY bit. C0MCTRLm.SET_RDY = 1 C0MCTRLm.
PAGE 1021
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Figure 20-40 shows the processing for a transmit message buffer during transmission (MT2 to MT0 bits of C0MCONFm register = 000B). Figure 20-40. Message Buffer Redefinition during Transmission START Transmit abort process Clear RDY bit. SET_RDY bit = 0 CLEAR_RDY bit = 1 RDY RDYbit= =0?0? No Yes Data frame Data frame or remote frame? Set C0MDATAxm, C0MDLCm registers. Clear RTR bit of C0MCONFm register. Set C0MIDLm and C0MIDHm registers.
PAGE 1022
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Figure 20-41 shows the processing for a transmit message buffer (C0MCONFm.MT2 to C0MCONFm.MT0 bits = 000B). Figure 20-41. Message Transmit Processing START No TRQ bit = 0? Yes Clear RDY bit. Set RDY bit = 0 Clear RDY bit = 1 RDY bit = 0? No Yes Data frame Data frame or remote frame? Remote frame Set RTR bit of C0MDLCm register and C0MCONFm register. Set C0MIDLm and C0MIDHm registers. Set C0MDATAxm, C0MDLCm registers.
PAGE 1023
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Figure 20-42 shows the processing for a transmit message buffer (C0MCONFm.MT2 to C0MCONFm.MT0 bits = 000B). Figure 20-42. ABT Message Transmit Processing START ABTTRG ABTTRGbit= =0?0? No Yes Clear RDY bit SET_RDY bit = 0 CLEAR_RDY bit = 1 RDY RDYbit == 0?0? No Yes Set C0MDATAxm register. Set C0MDLCm register. Clear RTR bit of C0MCONFm register. Set C0MIDLm and C0MIDHm registers. SetRDY RDYbit.
PAGE 1024
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Figure 20-43. Transmission via Interrupt (Using C0LOPT Register) Start Transmit completion interrupt servicing Read C0LOPT register. Clear RDY bit. Set RDY bit = 0 Clear RDY bit = 1 No RDY bit = 0? Yes Data frame Data frame or remote frame? Set C0MDATAxm, C0MDLCm registers. Clear RTR bit of C0MCONFm register. Set C0MIDLm and C0MIDHm registers. Remote frame Set C0MDLCm register. Set RTR bit of C0MCONFm register.
PAGE 1025
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Figure 20-44. Transmission via Interrupt (Using C0TGPT Register) START Transmit completion interrupt servicing Read C0TGPT register. No TOVF bit = 1? Yes Clear TOVF bit. Clear TOVF bit = 1 Clear RDY bit. Set RDY bit = 0 Clear RDY bit = 1 No RDY bit = 0? Set RDY bit. Set RDY bit = 1 Clear RDY bit = 0 Yes Data frame Data frame or remote frame? Set C0MDATAxm, C0MDLCm registers. Clear RTR bit of C0MCONFm register.
PAGE 1026
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Figure 20-45. Transmission via Software Polling START No CINTS0 bit = 1? Yes Clear CINTS0 bit. Clear CINTS0 bit = 1 Read C0TGPT register. No TOVF bit = 1? Yes Clear TOVF bit. Clear TOVF bit = 1 Clear RDY bit. Set RDY bit = 0 Clear RDY bit = 1 RDY bit = 0? No Set RDY bit. Set RDY bit = 1 Clear RDY bit = 0 Yes Data frame Set C0MDATAxm, C0MDLCm registers. Clear RTR bit of C0MCONFm register. Set C0MIDLm and C0MIDHm registers.
PAGE 1027
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Figure 20-46. Transmission Abort Processing (Other Than in Normal Operation Mode with ABT) START Clear TRQ bit. Set TRQ bit = 0 Clear TRQ bit = 1 Wait for a period of 11 CAN data bitsNote. TSTAT bit = 0? No Yes Read C0LOPT register. Message buffer to be aborted matches C0LOPT register? No Yes Transmission successful Transmit abort request was successful.
PAGE 1028
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Figure 20-47. Transmission Abort Processing Except for ABT Transmission (Normal Operation Mode with ABT) START Clear ABTTRG bit. SET_ABTTRG bit = 0 CLEAR_ABTTRG bit = 1 ABTTRG bit = 0? No Yes Clear TRQ bit. SET_TRQ bit = 0 CLEAR_TRQ bit = 1 Wait for a period of 11 CAN data Note bits. TSTAT bit = 0? No Yes Read C0LOPT register.
PAGE 1029
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Figure 20-48 (a) shows processing that does not skip resuming the transmission of a message that was interrupted when the transmission of an ABT message buffer was aborted. Figure 20-48 (a). ABT Transmission Abort Processing (Normal Operation Mode with ABT) START No TSTAT bit = 0? Yes Clear ABTTRG bit. Set ABTTRG bit = 0 Clear ABTTRG bit = 1 No ABTTRG bit = 0? Yes Clear TRQ bit of message buffer whose transmission was aborted.
PAGE 1030
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Figure 20-48 (b) shows the processing that does not skip resuming the transmission of a message that was interrupted when the transmission of an ABT message buffer was aborted. Figure 20-48 (b). ABT Transmission Abort Processing (Normal Operation Mode with ABT) START Clear TRQ bit of message buffer undergoing transmission. Clear ABTTRG bit.
PAGE 1031
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Figure 20-49. Reception via Interrupt (Using C0LIPT Register) START Receive completion interrupt Read C0LIPT register. Clear DN bit. Clear DN bit = 1 Read C0MDATAxm, C0MDLCm, C0MIDLm, and C0MIDHm registers. DN bit = 0 and MUC bit = 0Note No Yes Clear CINTS1 bit. Clear CINTS1 bit = 1 END Note Check the MUC and DN bits using one read access.
PAGE 1032
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Figure 20-50. Reception via Interrupt (Using C0RGPT Register) START Receive completion interrupt Read C0RGPT register. No ROVF bit = 1? Yes Clear ROVF bit. Clear ROVF bit = 1 Yes RHPM bit = 1? No Clear DN bit. Clear DN bit = 1 Read C0MDATAxm, C0MDLCm, C0MIDLm, and C0MIDHm registers. DN bit = 0 AND MUC bit = 0Note No Yes Read normal data. Read illegal data. END Note Check the MUC and DN bits using one read access. Remarks 1.
PAGE 1033
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Figure 20-51. Reception via Software Polling START No CINTS1 bit = 1? Yes Clear CINTS1 bit. Clear CINTS1 bit = 1 Read C0RGPT register No ROVF bit = 1? Yes Clear ROVF bit. Clear ROVF bit = 1 Yes RHPM bit = 1? No Clear DN bit. Clear DN bit = 1 Read C0MDATAxm, C0MDLCm, C0MIDLm, and C0MIDHm registers. DN bit = 0 AND MUC bit = 0Note No Yes Read normal data. Read illegal data. END Note Check the MUC and DN bits using one read access. Remarks 1.
PAGE 1034
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Figure 20-52. Setting CAN Sleep Mode/Stop Mode START (when PSMODE[1:0] = 00B) Set PSMODE0 bit SET_PSMODE1 = 1 CLEAR_PSMODE1 = 0 PSMODE0 = 1? No Yes CAN sleep mode Set PSMODE1 bit. SET_PSMODE1 = 1 CLEAR_PSMODE1 = 0 PSMODE1 = 1? No No Request CAN sleep mode again? Yes CAN stop mode Yes END Clear OPMODE. No INIT mode? Yes Access to registers other than the C0CTRL and C0GMCTRL registers. Set C0CTRL register. (Set OPMODE) Clear CINTS5 bit.
PAGE 1035
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Figure 20-53. Clear CAN Sleep/Stop Mode START CAN stop mode Clear PSMODE1 bit. Set PSMODE1 bit = 0 Clear PSMODE1 bit = 1 CAN sleep mode CAN sleep mode release by user Clear PSMODE0 bit.
PAGE 1036
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Figure 20-54. Bus-off Recovery (Other Than in Normal Operation Mode with ABT) START No BOFF bit = 1? Yes Clear all TRQ bitsNote. Set C0CTRL register. (clear OPMODE bit) Access to register other than C0CTRL and C0GMCTRL registers. Forced recovery from bus off? No Yes Set CCERC bit. Set CCERC bit = 1 Set C0CTRL register. (set OPMODE bit) Set C0CTRL register. (Set OPMODE bit) Wait for recovery from bus off.
PAGE 1037
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Figure 20-55. Bus-off Recovery (Normal Operation Mode with ABT) START No BOFF bit = 1? Yes Clear ABTTRG bit. Set ABTTRG bit = 0 Clear ABTTRG bit = 1 Clear all TRQ bitNote Set C0CTRL register. (Clear OPMODE bit.) Access to register other than C0CTRL and C0GMCTRL registers. Forced recovery from bus off? No Yes Set CCERC bit. Set CCERC bit = 1 Set C0CTRL register. (Set OPMODE.) Set C0CTRL register. (Set OPMODE bit.
PAGE 1038
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Figure 20-56. Normal Shutdown Process START INIT mode Clear GOM bit. Set GOM bit = 0 Clear GOM bit = 1 Shutdown successful GOM bit = 0, EFSD bit = 0 END R01UH0042EJ0500 Rev.5.
PAGE 1039
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Figure 20-57. Forced Shutdown Process START Set EFSD bit. Set EFSD bit = 1 Must be a continuous write. Clear GOM bit. Set GOM bit = 0 Clear GOM bit = 1 No GOM bit = 0? Yes Shutdown successful GOM bit = 0, EFSD bit = 0 End Caution Do not read- or write-access any registers by software between setting the EFSD bit and clearing the GOM bit. R01UH0042EJ0500 Rev.5.
PAGE 1040
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Figure 20-58. Error Handling START Error interrupt CINTS2 bit = 1? No Yes Check CAN module state. (read C0INFO register) Clear CINTS2 bit. Clear CINTS2 bit = 1 CINTS3 bit = 1? No CINTS4 bit = 1? No Yes Yes Check CAN protocol error state. (read C0LEC register) Clear CINTS4 bit. Clear CINTS4 bit = 1 Clear CINTS3 bit. Clear CINTS3 bit = 1 END R01UH0042EJ0500 Rev.5.
PAGE 1041
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Figure 20-59. Setting CPU Standby (from CAN Sleep Mode) START Set PSMODE0 bit. Set PSMODE0 bit = 1 Clear PSMODE0 bit = 0 PSMODE0 bit = 1? No Yes CAN sleep mode MBON bit = 0? Yes Set CPU standby mode. No CINTS5 bit 1? No Yes Clear PSMODE0 bit. Set PSMODE0 bit = 0 Clear PSMODE0 bit = 1 END Clear CINTS5 bit. Clear CINTS5 bit = 1 Note Check if the CPU is in the CAN sleep mode before setting it to the standby mode.
PAGE 1042
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER Figure 20-60. Setting CPU Standby (from CAN Stop Mode) START Set PSMODE0 bit. Set PSMODE0 bit = 1 Clear PSMODE0 bit = 0 PSMODE0 bit = 1? No Yes CAN sleep mode Set PSMODE1 bit. Set PSMODE1 bit = 1 Clear PSMODE1 bit = 0 No Clear PSMODE0 bit. Set PSMODE0 bit = 0 Clear PSMODE0 bit = 1 PSMODE1 bit = 1? Yes CAN stop mode Clear CINTS5 bitNote Clear CINTS5 bit = 1 MBON bit = 1? No Yes Set CPU standby mode.
PAGE 1043
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) CHAPTER 21 USB FUNCTION CONTROLLER (USBF) The V850ES/JG3-H and V850ES/JH3-H have an internal USB function controller (USBF) conforming to the Universal Serial Bus Specification. Data communication using the polling method is performed between the USB function controller and external host device by using a token-based protocol. 21.
PAGE 1044
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) 21.2 Configuration 21.2.1 Block diagram Figure 21-1.
PAGE 1045
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) 21.2.2 USB memory map The USB function controller seen from the CPU is assigned to the CS1 space in the microcontroller. The memory space is divided for use as follows. Table 21-1.
PAGE 1046
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) 21.3 External Circuit Configuration 21.3.1 Outline In USB transmission, when communication is performed with the host controller and function controller facing each other, pull-up/pull-down resistors must be connected to the USB signal (D+/D−) to identify the communication partner. Moreover in the V850ES/JG3-H and V850ES/JH3-H, series resistors must also be connected.
PAGE 1047
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) 21.3.2 Connection configuration Figure 21-3. Example of USB Function Controller Connection UVDD V850ES/JG3-H, V850ES/JH3-H Determine the pull-up resistor value in accordance with the buffer type (pull-down/pull-up) of the port pin to be used. P42/INTP10 UVDD IC1 P41 IC2 Connect a pull-up resistor to D+. 1.5 kΩ ±5%.
PAGE 1048
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (3) Detection of USB cable connection/disconnection The USB function controller (USBF) requires a VBUS input signal to recognize whether the USB cable is connected or disconnected, because the state of the USBF is controlled by hardware. The voltage from the USB host or HUB (5 V) is applied as the VBUS input signal when the USB cable VBUS is connected to the USB host or HUB while the USBF power is off.
PAGE 1049
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) 21.4 Cautions (1) Clock accuracy To operate the USB function controller, the internal clock (6 MHz external clock × internal clock multiplied by 8 = 48 MHz internal clock) or external clock (external clock input to UCLK pin (fUSB = 48 MHz)) must be used as the USB clock. When the internal clock is used as the USB clock, use a resonator with an accuracy of 6 MHz ±500 ppm (max.).
PAGE 1050
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) 21.5 Requests The USB standard has a request command that reports requests from the host device to the function device to execute response processing. The requests are received in the SETUP stage of control transfer, and most can be automatically processed via the hardware of the USB function controller (USBF). 21.5.
PAGE 1051
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Table 21-3.
PAGE 1052
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Notes 3. The SET_FEATURE request sets the UF0 device status register L (UF0DSTL) and UF0 EPn status register L (UF0EnSL) (n = 0 to 4, 7) when ACK is received in the status stage.
PAGE 1053
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (2) Processing The processing of an automatic request in the Default state, Addressed state, and Configured state is described below.
PAGE 1054
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (c) GET_DESCRIPTOR() request If the subject descriptor has a length that is a multiple of wMaxPacketSize, a Null packet is returned to indicate the end of the data stage. If the length of the descriptor at this time is less than the wLength value, the entire descriptor is returned; if the length of the descriptor is greater than the wLength value, the descriptor up to the wLength value is returned.
PAGE 1055
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (e) GET_STATUS() request A STALL response is made in the data stage if any of wValue, wIndex, or wLength is other than the values shown in Table 21-3. A STALL response is also made in the data stage if the target is an interface or an endpoint that does not exist.
PAGE 1056
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (g) SET_CONFIGURATION() request If any of wValue, wIndex, or wLength is other than the values shown in Table 21-3, a STALL response is made in the status stage. • Default state: The CONF bit of the UF0 mode status register (UF0MODS) and the UF0 configuration register (UF0CNF) are set to 1 if the specified configuration value is 1 when the SET_CONFIGURATION() request has been received.
PAGE 1057
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (i) SET_INTERFACE() request If wLength is other than the values shown in Table 21-3, if wIndex is other than the value set to the UF0 active interface number register (UF0AIFN), or if wValue is other than the value set to the UF0 active alternative setting register (UF0AAS), a STALL response is made in the status stage. • Default state: A STALL response is made in the status stage when the SET_INTERFACE() request has been received.
PAGE 1058
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) 21.6 Register Configuration 21.6.1 USB control registers (1) USB clock select register (UCKSEL) The UCKSEL register selects the operation clock of the USB controller. The UCKSEL register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
PAGE 1059
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (3) USB function select register (UHCKMSK) The UHCKMSK register controls the operation of the data-only RAM when the USB controller function is used. Even when the USB function controller is not being used, the data-only RAM can be used by setting the UHCKMSK register. The UHCKMSK register can be read or written in 8-bit or 1-bit units. Reset sets this register to 03H.
PAGE 1060
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) 21.6.
PAGE 1061
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (2/2) Address Function Register Name Symbol R/W Manipulatable Bits 1 8 Default Value 16 00200080H UF0 active interface number register UF0AIFN R/W √ 00H 00200082H UF0 active alternative setting register UF0AAS R/W √ 00H 00200084H UF0 alternative setting status register UF0ASS R √ 00H 00200086H UF0 endpoint 1 interface mapping register UF0E1IM R/W √ 00H 00200088H UF0 endpoint 2 interface mapping register
PAGE 1062
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (3) EPC request data register (1/13) Address Function Register Name Symbol R/W Manipulatable Bits 1 8 Default Value 16 00200144H UF0 device status register L UF0DSTL R/W √ 00H 0020014CH UF0 EP0 status register L UF0E0SL R/W √ 00H 00200150H UF0 EP1 status register L UF0E1SL R/W √ 00H 00200154H UF0 EP2 status register L UF0E2SL R/W √ 00H 00200158H UF0 EP3 status register L UF0E3SL R/W √ 00H 0020015CH
PAGE 1063
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (2/13) Address Function Register Name Symbol R/W Manipulatable Bits 1 002001CEH UF0 configuration/interface/endpoint descriptor 8 Default Value 16 UF0CIE4 R/W √ Undefined UF0CIE5 R/W √ Undefined UF0CIE6 R/W √ Undefined UF0CIE7 R/W √ Undefined UF0CIE8 R/W √ Undefined UF0CIE9 R/W √ Undefined UF0CIE10 R/W √ Undefined UF0CIE11 R/W √ Undefined UF0CIE12 R/W √ Undefined UF0CIE13 R/W √ Undefined
PAGE 1064
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (3/13) Address Function Register Name Symbol R/W Manipulatable Bits 1 002001FAH UF0 configuration/interface/endpoint descriptor 8 Default Value 16 UF0CIE26 R/W √ Undefined UF0CIE27 R/W √ Undefined UF0CIE28 R/W √ Undefined UF0CIE29 R/W √ Undefined UF0CIE30 R/W √ Undefined UF0CIE31 R/W √ Undefined UF0CIE32 R/W √ Undefined UF0CIE33 R/W √ Undefined UF0CIE34 R/W √ Undefined UF0CIE35 R/W √ Undef
PAGE 1065
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (4/13) Address Function Register Name Symbol R/W Manipulatable Bits 1 00200226H UF0 configuration/interface/endpoint descriptor 8 Default Value 16 UF0CIE48 R/W √ Undefined UF0CIE49 R/W √ Undefined UF0CIE50 R/W √ Undefined UF0CIE51 R/W √ Undefined UF0CIE52 R/W √ Undefined UF0CIE53 R/W √ Undefined UF0CIE54 R/W √ Undefined UF0CIE55 R/W √ Undefined UF0CIE56 R/W √ Undefined UF0CIE57 R/W √ Undef
PAGE 1066
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (5/13) Address Function Register Name Symbol R/W Manipulatable Bits 1 00200252H UF0 configuration/interface/endpoint descriptor 8 Default Value 16 UF0CIE70 R/W √ Undefined UF0CIE71 R/W √ Undefined UF0CIE72 R/W √ Undefined UF0CIE73 R/W √ Undefined UF0CIE74 R/W √ Undefined UF0CIE75 R/W √ Undefined UF0CIE76 R/W √ Undefined UF0CIE77 R/W √ Undefined UF0CIE78 R/W √ Undefined UF0CIE79 R/W √ Undef
PAGE 1067
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (6/13) Address Function Register Name Symbol R/W Manipulatable Bits 1 0020027EH UF0 configuration/interface/endpoint descriptor 8 Default Value 16 UF0CIE92 R/W √ Undefined UF0CIE93 R/W √ Undefined UF0CIE94 R/W √ Undefined UF0CIE95 R/W √ Undefined UF0CIE96 R/W √ Undefined UF0CIE97 R/W √ Undefined UF0CIE98 R/W √ Undefined UF0CIE99 R/W √ Undefined UF0CIE100 R/W √ Undefined UF0CIE101 R/W √ Und
PAGE 1068
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (7/13) Address Function Register Name Symbol R/W Manipulatable Bits 1 002002AAH UF0 configuration/interface/endpoint descriptor 8 Default Value 16 UF0CIE114 R/W √ Undefined UF0CIE115 R/W √ Undefined UF0CIE116 R/W √ Undefined UF0CIE117 R/W √ Undefined UF0CIE118 R/W √ Undefined UF0CIE119 R/W √ Undefined UF0CIE120 R/W √ Undefined UF0CIE121 R/W √ Undefined UF0CIE122 R/W √ Undefined UF0CIE123 R/W
PAGE 1069
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (8/13) Address Function Register Name Symbol R/W Manipulatable Bits 1 002002D6H UF0 configuration/interface/endpoint descriptor 8 Default Value 16 UF0CIE136 R/W √ Undefined UF0CIE137 R/W √ Undefined UF0CIE138 R/W √ Undefined UF0CIE139 R/W √ Undefined UF0CIE140 R/W √ Undefined UF0CIE141 R/W √ Undefined UF0CIE142 R/W √ Undefined UF0CIE143 R/W √ Undefined UF0CIE144 R/W √ Undefined UF0CIE145 R/W
PAGE 1070
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (9/13) Address Function Register Name Symbol R/W Manipulatable Bits 1 00200302H UF0 configuration/interface/endpoint descriptor 8 Default Value 16 UF0CIE158 R/W √ Undefined UF0CIE159 R/W √ Undefined UF0CIE160 R/W √ Undefined UF0CIE161 R/W √ Undefined UF0CIE162 R/W √ Undefined UF0CIE163 R/W √ Undefined UF0CIE164 R/W √ Undefined UF0CIE165 R/W √ Undefined UF0CIE166 R/W √ Undefined UF0CIE167 R/W
PAGE 1071
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (10/13) Address Function Register Name Symbol R/W Manipulatable Bits 1 0020032EH UF0 configuration/interface/endpoint descriptor 8 Default Value 16 UF0CIE180 R/W √ Undefined UF0CIE181 R/W √ Undefined UF0CIE182 R/W √ Undefined UF0CIE183 R/W √ Undefined UF0CIE184 R/W √ Undefined UF0CIE185 R/W √ Undefined UF0CIE186 R/W √ Undefined UF0CIE187 R/W √ Undefined UF0CIE188 R/W √ Undefined UF0CIE189 R/
PAGE 1072
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (11/13) Address Function Register Name Symbol R/W Manipulatable Bits 1 0020035AH UF0 configuration/interface/endpoint descriptor 8 Default Value 16 UF0CIE202 R/W √ Undefined UF0CIE203 R/W √ Undefined UF0CIE204 R/W √ Undefined UF0CIE205 R/W √ Undefined UF0CIE206 R/W √ Undefined UF0CIE207 R/W √ Undefined UF0CIE208 R/W √ Undefined UF0CIE209 R/W √ Undefined UF0CIE210 R/W √ Undefined UF0CIE211 R/
PAGE 1073
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (12/13) Address Function Register Name Symbol R/W Manipulatable Bits 1 00200386H UF0 configuration/interface/endpoint descriptor 8 Default Value 16 UF0CIE224 R/W √ Undefined UF0CIE225 R/W √ Undefined UF0CIE226 R/W √ Undefined UF0CIE227 R/W √ Undefined UF0CIE228 R/W √ Undefined UF0CIE229 R/W √ Undefined UF0CIE230 R/W √ Undefined UF0CIE231 R/W √ Undefined UF0CIE232 R/W √ Undefined UF0CIE233 R/
PAGE 1074
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (13/13) Address Function Register Name Symbol R/W Manipulatable Bits 1 002003B2H UF0 configuration/interface/endpoint descriptor 8 Default Value 16 UF0CIE246 R/W √ Undefined UF0CIE247 R/W √ Undefined UF0CIE248 R/W √ Undefined UF0CIE249 R/W √ Undefined UF0CIE250 R/W √ Undefined UF0CIE251 R/W √ Undefined UF0CIE252 R/W √ Undefined UF0CIE253 R/W √ Undefined UF0CIE254 R/W √ Undefined UF0CIE255 R/
PAGE 1075
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (4) Bridge register Address Function Register Name Symbol R/W Manipulatable Bits 1 8 Default Value 16 00200400H Bridge interrupt control register BRGINTT R/W √ 0000H 00200402H Bridge interrupt enable register BRGINTE R/W √ 0000H 00200404H EPC macro control register EPCCLT R/W √ 0000H 00200408H CPU I/F bus control register CPUBCTL R/W √ 0000H (5) DMA register Address Function Register Name Symbol R/W Ma
PAGE 1076
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) 21.6.3 EPC control registers (1) UF0 EP0NAK register (UF0E0N) This register controls NAK of Endpoint0 (except an automatically executed request). This register can be read or written in 8-bit units (however, bit 0 can only be read). It takes five USB clocks to reflect the status on this register after the UF0FIC0 and UF0FIC1 registers have been set.
PAGE 1077
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Next, the procedure of a SETUP transaction that uses IN/OUT tokens is explained below. (a) When IN token is used (except a request automatically executed by hardware) FW should be used to clear the PROT bit of the UF0IS1 register to 0 after receiving the CPUDEC interrupt and before reading data from the UF0E0ST register.
PAGE 1078
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (2) UF0 EP0NAKALL register (UF0E0NA) This register controls NAK to all the requests of Endpoint0. It is also valid for automatically executed requests. This register can be read or written in 8-bit units.
PAGE 1079
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (3) UF0 EPNAK register (UF0EN) This register controls NAK of endpoints other than Endpoint0. This register can be read or written in 8-bit units (however, bits 4, 1, and 0 can only be read). The BKO2NK bit can be written only when the BKO2NKM bit of the UF0ENM register is 1 and the BKO1NK bit can be written only when the BKO1NKM bit of the UF0ENM register is 1.
PAGE 1080
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (2/4) Bit position 3 Bit name BKO2NK Function This bit controls NAK to Endpoint4 (bulk 2 transfer (OUT)). 1: Transmit NAK. 0: Do not transmit NAK (default value). This bit is set to 1 only when the FIFO connected to the SIE side of the UF0BO2 register (64-byte FIFO of bank configuration) cannot receive data. It is cleared to 0 when a toggle operation is performed.
PAGE 1081
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (3/4) Bit position 1 Bit name BKI2NK Function This bit controls NAK to Endpoint3 (bulk 2 transfer (IN)). 1: Do not transmit NAK. 0: Transmit NAK (default value). This bit is cleared to 0 only when the FIFO connected to the SIE side of the UF0BI2 register (64-byte FIFO of bank configuration) cannot receive data.
PAGE 1082
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (4/4) Bit position 0 Bit name BKI1NK Function This bit controls NAK to Endpoint1 (bulk 1 transfer (IN)). 1: Do not transmit NAK. 0: Transmit NAK (default value). This bit is cleared to 0 only when the FIFO connected to the SIE side of the UF0BI1 register (64-byte FIFO of bank configuration) cannot receive data.
PAGE 1083
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (4) UF0 EPNAK mask register (UF0ENM) This register controls masking a write access to the UF0EN register. This register can be read or written in 8-bit units. Be sure to clear bits 7 to 4, 1, and 0 to “0”. If it is set to 1, the operation is not guaranteed.
PAGE 1084
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (5) UF0 SNDSIE register (UF0SDS) This register performs manipulation such as no handshake. It can directly manipulate the pins of SIE. This register can be read or written in 8-bit units. Be sure to clear bit 2 to “0”. If it is set to 1, the operation is not guaranteed.
PAGE 1085
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (6) UF0 CLR request register (UF0CLR) This register indicates the target of the received CLEAR_FEATURE request. This register is read-only, in 8-bit units. This register is meaningful only when an interrupt request is generated. Each bit is set to 1 after completion of the status stage, and automatically cleared to 0 when this register is read.
PAGE 1086
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (7) UF0 SET request register (UF0SET) This register indicates the target of the automatically processed SET_XXXX (except SET_INTERFACE) request. This register is read-only, in 8-bit units. This register is meaningful only when an interrupt request is generated. Each bit is set to 1 after completion of the status stage, and automatically cleared to 0 when this register is read.
PAGE 1087
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (8) UF0 EP status 0 register (UF0EPS0) This register indicates the USB bus status and the presence or absence of register data. This register is read-only, in 8-bit units. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1 to 4, 7) and the current setting of the interface.
PAGE 1088
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (2/2) Bit position 1 Bit name EP0W Function This bit indicates that data is in the UF0E0W register (FIFO). By setting the E0DED bit of the UF0DEND register to 1, the status in which data is in the UF0E0W register can be created even if data is not written to the register (Null data transmission).
PAGE 1089
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (9) UF0 EP status 1 register (UF0EPS1) This register indicates the USB bus status and the presence or absence of register data. This register is read-only, in 8-bit units. UF0EPS1 7 6 5 4 3 2 1 0 Address After reset RSUM 0 0 0 0 0 0 0 00200010H 00H Bit position 7 Bit name RSUM Function This bit indicates that the USB bus is in the Resume status. This bit is meaningful only when an interrupt request is generated.
PAGE 1090
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (10) UF0 EP status 2 register (UF0EPS2) This register indicates the USB bus status and the presence or absence of register data. This register is read-only, in 8-bit units. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1 to 4, 7) and the current setting of the interface.
PAGE 1091
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (11) UF0 INT status 0 register (UF0IS0) This register indicates the interrupt source. If the contents of this register are changed, the EPCINT0B signal becomes active. This register is read-only, in 8-bit units. If an interrupt request (INTUSBF0) is generated from USBF, the FW must read this register to identify the interrupt source.
PAGE 1092
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (2/2) Bit position 3 Bit name DMAED Function This bit indicates that the DMA end (TC) signal for Endpoint n (n = 1 to 4, 7) is active. 1: DMA end signal for Endpoint n has been input (interrupt request is generated). 0: DMA end signal for Endpoint n has not been input (default value). When this bit is set to 1, the DMA request signal for Endpoint n becomes inactive.
PAGE 1093
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (12) UF0 INT status 1 register (UF0IS1) This register indicates the interrupt source. If the contents of this register are changed, the EPCINT0B signal becomes active. This register is read-only, in 8-bit units. If an interrupt request (INTUSBF0) is generated from USBF, the FW must read this register to identify the interrupt source.
PAGE 1094
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (2/2) Bit position 4 Bit name E0ODT Function This bit indicates that data has been correctly received in the UF0E0R register. 1: Data is in UF0E0R register (interrupt request is generated). 0: Data is not in UF0E0R register (default value). This bit is automatically set to 1 by hardware when data has been correctly received. At the same time, the EP0R bit of the UF0EPS0 register is also set to 1.
PAGE 1095
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (13) UF0 INT status 2 register (UF0IS2) This register indicates the interrupt source. If the contents of this register are changed, the EPCINT1B signal becomes active. This register is read-only, in 8-bit units. If an interrupt request (INTUSBF0) is generated from USBF, the FW must read this register to identify the interrupt source.
PAGE 1096
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (14) UF0 INT status 3 register (UF0IS3) This register indicates the interrupt source. If the contents of this register are changed, the EPCINT1B signal becomes active. This register is read-only, in 8-bit units. If an interrupt request (INTUSBF0) is generated from USBF, the FW must read this register to identify the interrupt source.
PAGE 1097
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (2/2) Bit position 4, 0 Bit name BKOnDT Function These bits indicate that data has been correctly received in the UF0BOn register (Endpoint m). 1: Reception has been completed correctly (interrupt request is generated). 0: Reception has not been completed (default value). These bits are automatically set to 1 by hardware when data has been correctly received and the FIFO has been toggled.
PAGE 1098
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (15) UF0 INT status 4 register (UF0IS4) This register indicates the interrupt source. If the contents of this register are changed, the EPCINT2B signal becomes active. This register is read-only, in 8-bit units. If an interrupt request (INTUSBF0) is generated from USBF, the FW must read this register to identify the interrupt source.
PAGE 1099
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (16) UF0 INT mask 0 register (UF0IM0) This register controls masking of the interrupt sources indicated by the UF0IS0 register. This register can be read or written in 8-bit units. FW can mask occurrence of an interrupt request from USBF (INTUSBF0) by writing 1 to the corresponding bit of this register.
PAGE 1100
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (17) UF0 INT mask 1 register (UF0IM1) This register controls masking of the interrupt sources indicated by the UF0IS1 register. This register can be read or written in 8-bit units. FW can mask occurrence of an interrupt request from USBF (INTUSBF0) by writing 1 to the corresponding bit of this register.
PAGE 1101
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (18) UF0 INT mask 2 register (UF0IM2) This register controls masking of the interrupt sources indicated by the UF0IS2 register. This register can be read or written in 8-bit units. FW can mask occurrence of an interrupt request from USBF (INTUSBF0) by writing 1 to the corresponding bit of this register.
PAGE 1102
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (19) UF0 INT mask 3 register (UF0IM3) This register controls masking of the interrupt sources indicated by the UF0IS3 register. This register can be read or written in 8-bit units. FW can mask occurrence of an interrupt request from USBF (INTUSBF0) by writing 1 to the corresponding bit of this register.
PAGE 1103
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (20) UF0 INT mask 4 register (UF0IM4) This register controls masking of the interrupt sources indicated by the UF0IS4 register. This register can be read or written in 8-bit units. FW can mask occurrence of an interrupt request from USBF (INTUSBF0) by writing 1 to the corresponding bit of this register.
PAGE 1104
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (21) UF0 INT clear 0 register (UF0IC0) This register controls clearing the interrupt sources indicated by the UF0IS0 register. This register is write-only, in 8-bit units. If this register is read, the value FFH is read. FW can clear an interrupt source by writing 0 to the corresponding bit of this register. Even a bit that is automatically cleared to 0 by hardware can be cleared by FW before it is cleared by hardware.
PAGE 1105
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (22) UF0 INT clear 1 register (UF0IC1) This register controls clearing the interrupt sources indicated by the UF0IS1 register. This register is write-only, in 8-bit units. If this register is read, the value FFH is read. FW can clear an interrupt source by writing 0 to the corresponding bit of this register. Even a bit that is automatically cleared to 0 by hardware can be cleared by FW before it is cleared by hardware.
PAGE 1106
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (23) UF0 INT clear 2 register (UF0IC2) This register controls clearing the interrupt sources indicated by the UF0IS2 register. This register is write-only, in 8-bit units. If this register is read, the value FFH is read. FW can clear an interrupt source by writing 0 to the corresponding bit of this register. Even a bit that is automatically cleared to 0 by hardware can be cleared by FW before it is cleared by hardware.
PAGE 1107
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (24) UF0 INT clear 3 register (UF0IC3) This register controls clearing the interrupt sources indicated by the UF0IS3 register. This register is write-only, in 8-bit units. If this register is read, the value FFH is read. FW can clear an interrupt source by writing 0 to the corresponding bit of this register. Even a bit that is automatically cleared to 0 by hardware can be cleared by FW before it is cleared by hardware.
PAGE 1108
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (25) UF0 INT clear 4 register (UF0IC4) This register controls clearing the interrupt sources indicated by the UF0IS4 register. This register is write-only, in 8-bit units. If this register is read, the value FFH is read. FW can clear an interrupt source by writing 0 to the corresponding bit of this register. Even a bit that is automatically cleared to 0 by hardware can be cleared by FW before it is cleared by hardware.
PAGE 1109
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (26) UF0 INT & DMARQ register (UF0IDR) This register selects reporting via an interrupt request or starting DMA. This register can be read or written in 8-bit units. If data exists in either the UF0BO1 or UF0BO1 register, or if data can be written to the UF0BI1 or UF0BI2 register, this register selects whether it is reported to the FW by an interrupt request, or whether starting DMA is requested.
PAGE 1110
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (2/2) Bit position 1, 0 Bit name MODE1, MODE0 Function These bits select the DMA transfer mode. MODE1 MODE0 1 0 Mode Remark Demand DMA request signal becomes active as mode long as there is data. It becomes inactive if there is no more data. Other than above R01UH0042EJ0500 Rev.5.
PAGE 1111
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (27) UF0 DMA status 0 register (UF0DMS0) This register indicates the DMA status of Endpoint1 to Endpoint4. This register is read-only, in 8-bit units. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1 to 4) and the current setting of the interface.
PAGE 1112
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (28) UF0 DMA status 1 register (UF0DMS1) This register indicates the DMA status of Endpoint1 to Endpoint4. This register is read-only, in 8-bit units. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1 to 4) and the current setting of the interface. Each bit is automatically cleared to 0 when this register is read.
PAGE 1113
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (29) UF0 FIFO clear 0 register (UF0FIC0) This register clears each FIFO. This register is write-only, in 8-bit units. If this register is read, 00H is read. FW can clear the target FIFO by writing 1 to the corresponding bit of this register. The bit to which 1 has been written is automatically cleared to 0. Writing 0 to the bit is invalid.
PAGE 1114
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (30) UF0 FIFO clear 1 register (UF0FIC1) This register clears each FIFO. This register is write-only, in 8-bit units. If this register is read, 00H is read. FW can clear the target FIFO by writing 1 to the corresponding bit of this register. The bit to which 1 has been written is automatically cleared to 0. Writing 0 to the bit is invalid.
PAGE 1115
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (31) UF0 data end register (UF0DEND) This register reports the end of writing to the transmission system. This register is write-only, in 8-bit units (however, bits 7 and 6 can be read and written). If this register is read, 00H is read. FW can start data transfer of the target endpoint by writing 1 to the corresponding bit of this register. The bit to which 1 has been written is automatically cleared to 0.
PAGE 1116
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (2/2) Bit position 2, 1 Bit name BKInDED Function Set these bits to 1 when writing transmit data to the UF0BIn register has been completed. When these bits are set to 1, the FIFO is toggled as soon as possible, the BKInNK bit is set to 1, and data is transferred. 1: Transmit a short packet. 0: Do not transmit a short packet (default value). These bits control the FIFO on the CPU side.
PAGE 1117
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (32) UF0 GPR register (UF0GPR) This register controls USBF and the USB interface. This register is write-only, in 8-bit units. If this register is read, 00H is read. Be sure to clear bits 7 to 1 to “0”. FW can reset the USBF by writing 1 to bit 0 of this register. This bit is automatically cleared to 0 after 1 has been written to it. Writing 0 to this bit is invalid.
PAGE 1118
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (33) UF0 mode control register (UF0MODC) This register controls CPUDEC processing. This register can be read or written in 8-bit units. By setting each bit of this register, the setting of the UF0MODS register can be changed. The bit of this register is automatically cleared to 0 only at hardware reset and when the MRST bit of the UF0GRP register has been set to 1.
PAGE 1119
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (34) UF0 mode status register (UF0MODS) This register indicates the configuration status. This register is read-only, in 8-bit units. UF0MODS Bit position 6 7 6 5 4 3 2 1 0 Address After reset 0 CDCGD 0 MPACK DFLT CONF 0 0 00200078H 00H Bit name CDCGD Function This bit specifies whether CPUDEC processing is performed for the GET_DESCRIPTOR Configuration request.
PAGE 1120
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (35) UF0 active interface number register (UF0AIFN) This register sets the valid Interface number that correctly responds to the GET/SET_INTERFACE request. Because Interface 0 is always valid, Interfaces 1 to 4 can be selected. This register can be read or written in 8-bit units.
PAGE 1121
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (36) UF0 active alternative setting register (UF0AAS) This register specifies a link between the Interface number and Alternative Setting. This register can be read or written in 8-bit units. USBF of the V850ES/JG3-H and V850ES/JH3-H can set a five-series Alternative Setting (Alternate Setting 0, 1, 2, 3, and 4 can be defined) and a two-series Alternative Setting (Alternative Setting 0 and 1 can be defined) for one Interface.
PAGE 1122
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (37) UF0 alternative setting status register (UF0ASS) This register indicates the current status of the Alternative Setting. This register is read-only, in 8-bit units. Check this register when the SET_INT interrupt request has been issued. The value received by the SET_INTERFACE request is reflected on the UF0IFn register (n = 0 to 4) as well as on this register.
PAGE 1123
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (38) UF0 endpoint 1 interface mapping register (UF0E1IM) This register specifies for which Interface and Alternative Setting Endpoint1 is valid. This register can be read or written in 8-bit units.
PAGE 1124
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (39) UF0 endpoint 2 interface mapping register (UF0E2IM) This register specifies for which Interface and Alternative Setting Endpoint2 is valid. This register can be read or written in 8-bit units.
PAGE 1125
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (40) UF0 endpoint 3 interface mapping register (UF0E3IM) This register specifies for which Interface and Alternative Setting Endpoint3 is valid. This register can be read or written in 8-bit units.
PAGE 1126
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (41) UF0 endpoint 4 interface mapping register (UF0E4IM) This register specifies for which Interface and Alternative Setting Endpoint4 is valid. This register can be read or written in 8-bit units.
PAGE 1127
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (42) UF0 endpoint 7 interface mapping register (UF0E7IM) This register specifies for which Interface and Alternative Setting Endpoint7 is valid. This register can be read or written in 8-bit units.
PAGE 1128
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) 21.6.4 Data hold registers (1) UF0 EP0 read register (UF0E0R) The UF0E0R register is a 64-byte FIFO that stores the OUT data sent from the host in the data stage of control transfer to/from Endpoint0. This register is read-only, in 8-bit units. A write access to this register is ignored. The hardware automatically transfers data to the UF0E0R register when it has received the data from the host.
PAGE 1129
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-4.
PAGE 1130
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (3) UF0 EP0 setup register (UF0E0ST) The UF0E0ST register holds the SETUP data sent from the host. This register is read-only, in 8-bit units. A write access to this register is ignored. The UF0E0ST register always writes data when a SETUP transaction has been received. The hardware sets the PROT bit of the UF0IS1 register when it has correctly received the SETUP transaction.
PAGE 1131
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-5.
PAGE 1132
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (4) UF0 EP0 write register (UF0E0W) The UF0E0W register is a 64-byte FIFO that stores the IN data (passes it to SIE) sent to the host in the data stage to Endpoint0. This register is write-only, in 8-bit units. When this register is read, 00H is read. The hardware transmits data to the USB bus in synchronization with an IN token only when the EP0NKW bit of the UF0E0N register is set to 1 (when NAK is not transmitted).
PAGE 1133
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-6.
PAGE 1134
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (5) UF0 bulk-out 1 register (UF0BO1) The UF0BO1 register is a 64-byte × 2 FIFO that stores data for Endpoint2. This register consists of two banks of 64-byte FIFOs each of which performs a toggle operation and repeatedly connects the buses on the SIE and CPU sides. The toggle operation takes place when data is in the FIFO on the SIE side and when no data is in the FIFO on the CPU side (counter value = 0).
PAGE 1135
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-7.
PAGE 1136
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-7.
PAGE 1137
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (6) UF0 bulk-out 1 length register (UF0BO1L) The UF0BO1L register stores the length of the data held by the UF0BO1 register. This register is read-only, in 8-bit units. A write access to this register is ignored. The UF0BO1L register always updates the received data length while it is receiving data. If the final transfer is abnormal reception, the UF0BO1L register is cleared to 00H, and an interrupt request is not generated.
PAGE 1138
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (7) UF0 bulk-out 2 register (UF0BO2) The UF0BO2 register is a 64-byte × 2 FIFO that stores data for Endpoint4. This register consists of two banks of 64-byte FIFOs each of which performs a toggle operation and repeatedly connects the buses on the SIE and CPU sides. The toggle operation takes place when data is in the FIFO on the SIE side and when no data is in the FIFO on the CPU side (counter value = 0).
PAGE 1139
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-8.
PAGE 1140
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-8.
PAGE 1141
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (8) UF0 bulk-out 2 length register (UF0BO2L) The UF0BO2L register stores the length of the data held by the UF0BO2 register. This register is read-only, in 8-bit units. A write access to this register is ignored. The UF0BO2L register always updates the received data length while it is receiving data. If the final transfer is abnormal reception, the UF0BO2L register is cleared to 00H, and an interrupt request is not generated.
PAGE 1142
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-9.
PAGE 1143
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-9.
PAGE 1144
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-9.
PAGE 1145
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (10) UF0 bulk-in 2 register (UF0BI2) The UF0BI2 register is a 64-byte × 2 FIFO that stores data for Endpoint3. This register consists of two banks of 64-byte FIFOs each of which performs a toggle operation and repeatedly connects the buses on the SIE and CPU sides.
PAGE 1146
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-10.
PAGE 1147
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-10.
PAGE 1148
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-10.
PAGE 1149
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (11) UF0 interrupt 1 register (UF0INT1) The UF0INT1 register is an 8-byte FIFO that stores data for Endpoint7 (to be passed to SIE). This register is write-only, in 8-bit units. When this register is read, 00H is read. The hardware transmits data to the USB bus in synchronization with the IN token for Endpoint7 only when the IT1NK bit of the UF0EN register is set to 1 (when NAK is not transmitted).
PAGE 1150
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-11.
PAGE 1151
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) 21.6.5 EPC request data registers (1) UF0 device status register L (UF0DSTL) This register stores the value that is to be returned in response to the GET_STATUS Device request. This register can be read or written in 8-bit units. The hardware automatically transmits the contents of this register to the host when it has received the GET_STATUS Device request.
PAGE 1152
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (2) UF0 EP0 status register L (UF0E0SL) This register stores the value that is to be returned in response to the GET_STATUS Endpoint0 request. This register can be read or written in 8-bit units. Note, however, that data can be written to this register only when the EP0NKA bit is set to 1. If an error occurs in USBF, the E0HALT bit is set to 1 by FW.
PAGE 1153
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (3) UF0 EP1 status register L (UF0E1SL) This register stores the value that is to be returned in response to the GET_STATUS Endpoint1 request. This register can be read or written in 8-bit units. Note, however, that data can be written to this register only when the EP0NKA bit is set to 1. If an error occurs in Endpoint1, the E1HALT bit is set to 1.
PAGE 1154
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (4) UF0 EP2 status register L (UF0E2SL) This register stores the value that is to be returned in response to the GET_STATUS Endpoint2 request. This register can be read or written in 8-bit units. Note, however, that data can be written to this register only when the EP0NKA bit is set to 1. If an error occurs in Endpoint2, the E2HALT bit is set to 1.
PAGE 1155
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (5) UF0 EP3 status register L (UF0E3SL) This register stores the value that is to be returned in response to the GET_STATUS Endpoint3 request. This register can be read or written in 8-bit units. Note, however, that data can be written to this register only when the EP0NKA bit is set to 1. If an error occurs in Endpoint3, the E3HALT bit is set to 1.
PAGE 1156
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (6) UF0 EP4 status register L (UF0E4SL) This register stores the value that is to be returned in response to the GET_STATUS Endpoint4 request. This register can be read or written in 8-bit units. Note, however, that data can be written to this register only when the EP0NKA bit is set to 1. If an error occurs in Endpoint4, the E4HALT bit is set to 1.
PAGE 1157
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (7) UF0 EP7 status register L (UF0E7SL) This register stores the value that is to be returned in response to the GET_STATUS Endpoint7 request. This register can be read or written in 8-bit units. Note, however, that data can be written to this register only when the EP0NKA bit is set to 1. If an error occurs in Endpoint7, the E7HALT bit is set to 1.
PAGE 1158
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (8) UF0 address register (UF0ADRS) This register stores the device address. This register is read-only, in 8-bit units. The device address sent by the SET_ADDRESS request is analyzed and the resultant value is automatically written to this register. If the SET_ADDRESS request is processed by FW, the value of this register is reflected as the device address when the SUCCESS signal is received in the status stage.
PAGE 1159
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (9) UF0 configuration register (UF0CNF) This register stores the value that is to be returned in response to the GET_CONFIGURATION request. This register is read-only, in 8-bit units. When the SET_CONFIGURATION request is received, its wValue is automatically written to this register. When a change of the value of this register from 00H to other than 00H is detected, the CONF bit of the UF0MODS register is set to 1.
PAGE 1160
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (10) UF0 interface 0 register (UF0IF0) This register stores the value that is to be returned in response to the GET_INTERFACE wIndex = 0 request. This register is read-only, in 8-bit units. When the SET_INTERFACE request is received, its wValue is automatically written to this register. If the SET_INTERFACE request is processed by FW, wIndex and wValue are decoded, and the setting of endpoint is automatically changed.
PAGE 1161
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (11) UF0 interface 1 to 4 registers (UF0IF1 to UF0IF4) These registers store the value that is to be returned in response to the GET_INTERFACE wIndex = n request (n = 1 to 4). These registers are read-only, in 8-bit units. When the SET_INTERFACE request is received, its wValue is automatically written to these registers. These registers are invalidated according to the setting of the UF0AIFN and UF0AAS registers.
PAGE 1162
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (12) UF0 descriptor length register (UF0DSCL) This register stores the length of the value that is to be returned in response to the GET_DESCRIPTOR Configuration request. The value of this register is the number of bytes of all the descriptors set by the UF0CIEn register minus 1 (n = 0 to 255).
PAGE 1163
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (13) UF0 device descriptor registers 0 to 17 (UF0DD0 to UF0DD17) These registers store the value to be returned in response to the GET_DESCRIPTOR Device request. These registers can be read or written in 8-bit units. However, data can be written to these registers only when the EP0NKA bit is set to 1. Cautions 1.
PAGE 1164
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (14) UF0 configuration/interface/endpoint descriptor registers 0 to 255 (UF0CIE0 to UF0CIE255) These registers store the value to be returned in response to the GET_DESCRIPTOR Configuration request. These registers can be read or written in 8-bit units. However, data can be written to these registers only when the EP0NKA bit is set to 1. Descriptor information of up to 256 bytes can be stored in these registers.
PAGE 1165
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Table 21-7.
PAGE 1166
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) 21.6.6 Bridge register (1) Bridge interrupt control register (BRGINTT) The BRGINTT register controls the DMA transfer status of the interrupt generate status, and each end point (EP1 to EP4) from EPC to bridge circuit. The BRGINTT register can be read or written in 16-bit units.
PAGE 1167
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (2) Bridge interrupt enable register (BRGINTE) The BRGINTE register controls whether the interrupt generated in the bridge circuit is enabled or disabled. The BRGINTE register can be read or written in 16-bit units.
PAGE 1168
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (3) EPC macro control register (EPCCLT) The EPCCLT register controls the reset generator to the EPC macro. The EPCCLT register can be read or written in 16-bit units. After reset: 0000H EPCCLT Bit position 0 R/W Address: 00200404H 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 EPCRST Bit name EPCRST Function Setting the reset occurs to EPC.
PAGE 1169
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (4) CPU I/F bus control register (CPUBCTL) The CPUBCTL register controls the interface between bridge circuit and CPU. The CPUBCTL register can be read or written in 16-bit units.
PAGE 1170
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) 21.6.7 DMA register (1) EPn DMA control register 1 (UF0E1DC1 to UF0E4DC1) The UF0E1DC1 to UF0E4DC1 register controls the DMA transfer of end point n (EPn). (n = 1 to 4) The UF0E1DC1 to UF0E4DC1 register can be read or written in 16-bit units.
PAGE 1171
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (2/2) Bit position 5 to 3 Bit name EPnBULK2, Function Shown the status the state machine “BIN_STATE” for bulk transfer of the internal bridge EPnBULK1, EPnBULK0 2 EPnSTOP EPnBULK2 EPnBULK1 EPnBULK0 ”BIN_STATE” status 0 0 0 BIN_IDLE 0 0 1 BIN_CPU 0 1 0 BIN_EPC 0 1 1 BIN_CMP 1 0 0 BIN_END Showing the status (end factor of DMA transfer) of DMA transfer end from EPC 0: End of DMA transfer by EPn_TCNT value “0” 1
PAGE 1172
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (2) EPn DMA control register 2 (UF0E1DC2 to UF0E4DC2) The UF0E1DC2 to UF0E4DC2 register controls the DMA transfer of end point n (EPn). (n = 1 to 4) The UF0E1DC2 to UF0E4DC2 register can be read or written in 16-bit units.
PAGE 1173
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (2/2) Bit position 15 to 0 Bit name Function EPnTCNT15 to Setting the number of byte to DMA transfer in EPn. EPnTCNT0 End the DMA transfer after the value of EPn_TCNT is “0” to decrement each transfer. Cautions 1. Set this register when EPn_DMAEN = 0. 2. Setting this register to “0” is prohibited. Be sure to set this register +1 value for the value of DMA transfer count register DBC0 to DBC3. 3.
PAGE 1174
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) 21.6.8 Bulk-in register (1) UF0 EP1 bulk-in transfer data register (UF0EP1BI) The UF0EP1BI register writes the bulk-in transfer data of EP1. The UF0EP1BI register can be read or written in 8-bit or 16-bit units.
PAGE 1175
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) 21.6.9 Bulk-out register (1) UF0 EP2 bulk-out transfer data register (UF0EP2BO) The UF0EP2BO register writes the bulk-out transfer data of EP2. The UF0EP2BO register can be read or written in 8-bit or 16-bit units.
PAGE 1176
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (2) UF0 EP4 bulk-out transfer data register (UF0EP4BO) The UF0EP4BO register writes the bulk-out transfer data of EP4. The UF0EP4BO register can be read or written in 8-bit or 16-bit units.
PAGE 1177
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) 21.6.10 Peripheral control registers (1) USBF DMA request enable register (UFDRQEN) The UFDRQEN register specifies the DMA channel to be used and the endpoint to be transferred. The UFDRQEN register can be read or written in 8-bit or 16-bit units.
PAGE 1178
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (2/2) Bit position Bit name 13, 9, 5, 1 RQ1UR3E, Specify the endpoint n (EPn) to be transferred by DMA channel 1.
PAGE 1179
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) The following flowcharts illustrate the program execution when the host is disconnected and then reconnected, and the program execution when power is supplied. Figure 21-12.
PAGE 1180
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-13.
PAGE 1181
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) 21.7 STALL Handshake or No Handshake Errors of USBF are defined to be handled as follows.
PAGE 1182
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) 21.8 Register Values in Specific Status Table 21-8. Register Values in Specific Status (1/2) Register Name After CPU Reset (RESET) After Bus Reset UF0E0N register 00H Value is held. UF0E0NA register 00H Value is held. UF0EN register 00H Value is held. UF0ENM register 00H Value is held. UF0SDS register 00H Value is held. UF0CLR register 00H Value is held. UF0SET register 00H Value is held.
PAGE 1183
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Table 21-8. Register Values in Specific Status (2/2) Register Name After CPU Reset (RESET) After Bus Reset UF0E3IM register 00H Value is held. UF0E4IM register 00H Value is held. UF0E7IM register 00H UF0E0R register Undefined UF0E0L register 00H UF0E0ST register 00H UF0E0W register Undefined UF0BO1 register Value is held. Note 1 Value is held. Value is held. 00H Note 1 Value is held. Note 1 Value is held.
PAGE 1184
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) 21.9 FW Processing The following FW processing is performed.
PAGE 1185
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Table 21-9. FW-Supported Standard Requests Request CLEAR_FEATURE Reception Processing/ Side Frequency Interface Explanation Automatic STALL It is considered that this request does not come to Interface response because there is no function selector value, though it is reserved for bmRequestType. When this request is received, the hardware makes an automatic STALL response.
PAGE 1186
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) 21.9.1 Initialization processing Initialization processing is executed in the following two ways. • Initialization of request data register • Setting of interrupt When a request data register is initialized, data for the GET_XXXX request to which a value is to be automatically returned is written and an endpoint is allocated to an interface.
PAGE 1187
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-15. Initialization Settings of Request Data Register UF0DSTL register = 0XH The value of 0XH depends on the power supply method. • SFPW = 1: Self-powered • SFPW = 0: Bus-powered UF0EnSL register = 00H n = 0 to 4, or 7. Setting is unnecessary if the target endpoint is not used. Setting of UF0DSCL register Input the total number of bytes of the UF0CIEa register.
PAGE 1188
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-17. Setting of Interrupt START Setting of UF0IMn register Mask the interrupt source to avoid issuance of an unnecessary interrupt request (INTUSBF0). END Remark n = 0 to 4 R01UH0042EJ0500 Rev.5.
PAGE 1189
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) 21.9.2 Interrupt servicing The following flowchart illustrates how an interrupt is serviced. Figure 21-18. Interrupt Servicing START INTUSBF0 active (n = 0 to 4) Reading UF0ISn register Target bit of UF0ICn register = 0 Servicing interrupt END Remark ♦: Processing by hardware The following bits of the UF0ISn register are automatically cleared by hardware when a given condition is satisfied (n = 0 to 4).
PAGE 1190
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) 21.9.3 USB main processing USB main processing involves processing USB transactions. The types of transactions to be processed are as follows.
PAGE 1191
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-19. Automatically Processed Requests for Control Transfer START Receiving SETUP token Decoding request CLEAR_FEATURE? Yes CLEAR_FEATURE processing No : See Figure 21-20 CLEAR_FEATURE Processing. Yes SET_FEATURE? SET_FEATURE processing No : See Figure 21-21 SET_FEATURE Processing. Yes SET_CONFIGURATION? SET_CONFIGURATION processing No SET_INTERFACE? : See Figure 21-22 SET_CONFIGURATION Processing.
PAGE 1192
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-20. CLEAR_FEATURE Processing UF0CLR register = 0XH Set the corresponding bit for the value of 0XH. The EPHALT bit of the UF0IS0 register is cleared to 0 only when all Halt Features are cleared. CLRRQ = 1 (UF0IS0) Clearing UF0DSTL register Clearing UF0EnSL register HALTn = 0 (UF0EPS2) Remarks 1. n = 0 to 4, 7 2. ♦: Processing by hardware R01UH0042EJ0500 Rev.5.
PAGE 1193
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-21. SET_FEATURE Processing UF0SET register = 0XH Set the corresponding bit for the value of 0XH. The EPHALT bit of the UF0IS0 register is not set to 1 by setting the UF0DSTL register. SETRQ = 1 (UF0IS0) Setting UF0DSTL register Setting UF0EnSL register HALTn = 1 (UF0EPS2) EPHALT = 1 (UF0IS0) Remarks 1. n = 0 to 4, 7 2. ♦: Processing by hardware R01UH0042EJ0500 Rev.5.
PAGE 1194
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-22. SET_CONFIGURATION Processing SETCON = 1 (UF0SET) SETRQ = 1 (UF0IS0) CONF = 1 (UF0MODS) Setting UF0CNF register Remark ♦: Processing by hardware Figure 21-23. SET_INTERFACE Processing SETINT = 1 (UF0IS4) Setting UF0ASS register Setting UF0IFn register Remarks 1. n = 0 to 4 2. ♦: Processing by hardware R01UH0042EJ0500 Rev.5.
PAGE 1195
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (3) CPUDEC request for control transfer The CPUDEC request can be classified into three types of processing: control transfer (write), control transfer (read), and control transfer (without data). Control transfer (write) indicates a request that uses the OUT transaction in the data stage (e.g., SET_DESCRIPTOR), and control transfer (read) indicates a request that uses the IN transaction in the data stage (e.g., GET_DESCRIPTOR).
PAGE 1196
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-24. CPUDEC Request for Control Transfer (2/12) (a) Token phase (2/2) A It is judged whether the request decoded by the device is supported.
PAGE 1197
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-24. CPUDEC Request for Control Transfer (3/12) (b) Control transfer (read) (1/4) B CPUDEC = 1? (UF0IS1) No Yes Transmitting NAK E0IN = 1 (UF0IS1) INTUSBF0 active Reading UF0ISn register E0IN = 1? (UF0IS1) Yes No Illegal processing E0INM = 1 (UF0IM1) I FW request decode If return data greater than the FIFO size exists, it is divided into FIFO size units and sequentially written, starting from the lowest data byte.
PAGE 1198
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-24 CPUDEC Request for Control Transfer (4/12) (b) Control transfer (read) (2/4) F No FIFO full? E0DED = 1 (UF0DEND) Yes EP0NKW = 1 (UF0E0N) PROT = 1? (UF0IS1) Yes EP0WC = 1 (UF0FIC0) No G No IN token received? Yes Transmitting data of UF0E0W register No ACK received? Yes H Remark ♦: Processing by hardware R01UH0042EJ0500 Rev.5.
PAGE 1199
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-24. CPUDEC Request for Control Transfer (5/12) (b) Control transfer (read) (3/4) H E0INDT = 1 (UF0IS1) EP0NKW = 0 (UF0E0N) INTUSBF0 active Reading UF0ISn register E0INDT = 1? (UF0IS1) No Yes No transmit data? Illegal processing No I Yes E0INDTC = 0 (UF0IC1) Data of Null packet received? No Yes STG = 1 (UF0IS1) J Remarks 1. n = 0, 1 2. ♦: Processing by hardware R01UH0042EJ0500 Rev.5.
PAGE 1200
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-24. CPUDEC Request for Control Transfer (6/12) (b) Control transfer (read) (4/4) J INTUSBF0 active Reading UF0ISn register STG = 1? (UF0IS1) No Yes Illegal processing STGM = 1 (UF0IM1) Transmitting ACK SUCES = 1 (UF0IS1) INTUSBF0 active Reading UF0ISn register SUCES = 1? (UF0IS1) Yes No Illegal processing SUCESC = 0 (UF0IC1) E0INC = 0 (UF0IC1) CPUDECM = 0 (UF0IM1) E0INM = 0 (UF0IM1) END Remarks 1. n = 0, 1 2.
PAGE 1201
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-24. CPUDEC Request for Control Transfer (7/12) (c) Control transfer (write) (1/4) C OUT token received? No Yes Writing UF0E0R register Normal reception? No Yes Clearing UF0E0R register E0ODT = 1 (UF0IS1) EP0R = 1 (UF0EPS0) EP0NKR = 1 (UF0E0N) INTUSBF0 active Reading UF0ISn register PROT = 1? (UF0IS1) No K Yes EP0RC = 1 (UF0FIC0) G Remarks 1. n = 0, 1 2. ♦: Processing by hardware R01UH0042EJ0500 Rev.5.
PAGE 1202
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-24. CPUDEC Request for Control Transfer (8/12) (c) Control transfer (write) (2/4) K E0ODT = 1? (UF0IS1) No Yes Illegal processing Updating data length of UF0E0L register Reading UF0E0R register UF0E0L register data is read up to the value read by the UF0E0R register.
PAGE 1203
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-24. CPUDEC Request for Control Transfer (9/12) (c) Control transfer (write) (3/4) L STG = 1 (UF0IS1) E0IN = 1 (UF0IS1) INTUSBF0 active Reading UF0ISn register PROT = 1? (UF0IS1) Yes No Clearing read data G STG = 1? (UF0IS1) No Yes Illegal processing Request processing EP0WC = 1 (UF0FIC0) E0DED = 1 (UF0DEND) M Remarks 1. n = 0, 1 2. ♦: Processing by hardware R01UH0042EJ0500 Rev.5.
PAGE 1204
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-24.
PAGE 1205
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-24. CPUDEC Request for Control Transfer (11/12) (d) Control transfer (without data stage) (1/2) D IN token of status phase IN token received? No Yes E0IN = 1 (UF0IS1) STG = 1 (UF0IS1) INTUSBF0 active Reading UF0ISn register PROT = 1? (UF0IS1) Yes No Request processing aborted G STG = 1? (UF0IS1) Yes No Illegal processing EP0WC = 1 (UF0FIC0) E0DED = 1 (UF0DEND) N Remarks 1. n = 0, 1 2.
PAGE 1206
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-24.
PAGE 1207
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (4) Processing for bulk transfer (IN) Bulk transfer (IN) is allocated to Endpoint1 and Endpoint3. The flowchart shown below illustrates how Endpoint1 is controlled. Endpoint3 can also be controlled in the same sequence. To use this flowchart as the control flow of Endpoint3, therefore, read the bit names of Endpoint1 in the flowchart as those of Endpoint3. R01UH0042EJ0500 Rev.5.
PAGE 1208
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-25. Processing for Bulk Transfer (IN) (Endpoint1) START IN token received? No Yes BKI1IN = 1 (UF0IS2) Returning NAK INTUSBF0 active Reading UF0ISn register BKI1IN = 1? (UF0IS2) No Yes Illegal processing BKI1INM = 1 (UF0IM2) Writing UF0BI1 register Yes If return data greater than the FIFO size exists, it is divided into FIFO size units and sequentially written, starting from the lowest data byte.
PAGE 1209
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-26. Parallel Processing by Hardware IN token received? No Yes Transmitting data of UF0BI1 register ACK received? No Yes BKI1NK = 0 (UF0EN) No transmit data? No Yes Remark ♦: Processing by hardware R01UH0042EJ0500 Rev.5.
PAGE 1210
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (5) Processing for bulk transfer (OUT) Bulk transfer (OUT) is allocated to Endpoint2 and Endpoint4. The flowchart shown below illustrates how Endpoint2 is controlled. Endpoint4 can also be controlled in the same sequence. To use this flowchart as the control flow of Endpoint4, therefore, read the bit names of Endpoint2 in the flowchart as those of Endpoint4. R01UH0042EJ0500 Rev.5.
PAGE 1211
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-27.
PAGE 1212
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) During bulk transfer (OUT), more data may be transmitted from the host than expected by the system. Endpoint2 and Endpoint4 for bulk transfer (OUT) of the V850ES/JG3-H and V850ES/JH3-H consist of two 64-byte buffers so that NAK responses are suppressed as much as possible and data can be read from the CPU side even while the bus side is being accessed as the transfer rate of the USB bus increases.
PAGE 1213
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-28.
PAGE 1214
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-28. Processing If More Data Than Expected by System Is Transmitted (Endpoint2) (2/2) I Reading UF0BO1 register UF0BO1 register data is read up to the value read by the UF0BO1L register. Data length other than 0? Yes No Data length = Data length – 1 BKO1FL = 0 (UF0IS3) Updating data length of UF0BO1L register Reading UF0BO1 register UF0BO1 register data is read up to the value read by the UF0BO1L register.
PAGE 1215
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (6) Processing for interrupt transfer (IN) Interrupt transfer (IN) is allocated to Endpoint7. The flowchart is shown in Figure 21-29. Figure 21-29.
PAGE 1216
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) 21.9.4 Suspend/Resume processing How Suspend/Resume processing is performed differs depending on the configuration of the system. One example is given below. Figure 21-30.
PAGE 1217
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-30. Example of Suspend/Resume Processing (2/3) (b) Example of Resume processing START Resume detected? No Yes RSUSPD = 1 (UF0IS0) RSUM = 0 (UF0EPS1) INTUSBF0 active Reading UF0ISn register RSUSPD = 1? (UF0IS0) No Yes Illegal processing Reading UF0EPS1 register RSUM = 0? (UF0EPS1) Yes No Illegal processing FW Resume processing RSUSPDC = 0 (UF0IC0) END Remarks 1. n = 0, 1 2.
PAGE 1218
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-30. Example of Suspend/Resume Processing (3/3) (c) Example of Resume processing (when supply of USB clock to USBF is stopped) START Resume detected? No Yes INTUSBF1 active Executing interrupt servicing Supplying USB clock FW Resume processing END Remark ♦: Processing by hardware R01UH0042EJ0500 Rev.5.
PAGE 1219
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) 21.9.5 Processing after power application The processing to be performed after power application differs depending on the configuration of the system. One example is given below. Figure 21-31.
PAGE 1220
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-31.
PAGE 1221
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-31.
PAGE 1222
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) 21.9.6 Receiving data for bulk transfer (OUT) in DMA mode Bulk transfer (OUT) is allocated to Endpoint2 and Endpoint4. The flowchart shown below illustrates how Endpoint2 is controlled when DMA is used. Endpoint4 can also be controlled in the same sequence. To use this flowchart as the control flow of Endpoint4, therefore, read the bit names of Endpoint2 in the flowchart as those of Endpoint4.
PAGE 1223
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) (1) Initial settings for a bulk transfer (OUT: EP2, EP4) (a) Initial settings for DMAC - The DSAn registers (n = 0 to 3) are set to 00210000H (for EP2) or 00220000H (for EP4). - The DADCn registers (n = 0 to 3) are set to 0080H. (8-bit transfer, transfer source address: fixed, transfer destination address: incremental) - The DTFRn registers (n = 0 to 3) are set to 0000H.
PAGE 1224
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-32.
PAGE 1225
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-32.
PAGE 1226
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-32. DMA Processing by Bulk Transfer (OUT) (3/3) (2) DMA channel 2 transfer completed? No Yes INTUSBF0 interrupt occurred? DMA channel 2 transfer completion TC2 = 1 (DCHC2) DQBO1MS = 0 (UF0IDR) No An interrupt occurred when receiving Endpoint2 data.
PAGE 1227
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) 21.9.7 Transmitting data for bulk transfer (IN) in DMA mode Bulk transfer (IN) is allocated to Endpoint1 and Endpoint3. The flowchart shown below illustrates how Endpoint1 is controlled when DMA is used. Endpoint3 can also be controlled in the same sequence. To use this flowchart as the control flow of Endpoint3, therefore, read the bit names of Endpoint1 in the flowchart as those of Endpoint3.
PAGE 1228
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-33. DMA Processing by Bulk Transfer (IN) (1/4) START (5) Setting MODEx (UF0IDR) DQBI1MS = 1 (UF0IDR) MODE1, MODE0 = 10: Demand mode (3) FIFO on CPU side full? Yes No DQE1 = 1 (UF0DMS0) DMA request for Endpoint1 active If return data greater than the FIFO size exists, it is divided into FIFO size units, and sequentially written, starting from the lowest data byte.
PAGE 1229
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-33. DMA Processing by Bulk Transfer (IN) (2/4) (2) BKI1NK = 1 (UF0EN)Note BKI1DT = 1 (UF0IS2)Note DQE1 = 0 (UF0DMS0) DMA request for Endpoint1 inactive (3) Parallel processing by hardware : See Figure 21-26 Parallel Processing by Hardware. END Note The timing of the bit value changes depending on the status on the SIE side. Remark ♦: Processing by hardware R01UH0042EJ0500 Rev.5.
PAGE 1230
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-33.
PAGE 1231
V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF) Figure 21-33 DMA Processing by Bulk Transfer (IN) (4/4) (4) FIFO full? No Yes BKI1T = 1? (UF0DEND) No Yes Data error? No DMAEDC = 0 (UF0IC0) (5) Parallel processing by hardware Yes : See Figure 21-26 Parallel Processing by Hardware.
PAGE 1232
V850ES/JG3-H, V850ES/JH3-H CHAPTER 22 DMA FUNCTION (DMA CONTROLLER) CHAPTER 22 DMA FUNCTION (DMA CONTROLLER) The V850ES/JG3-H and V850ES/JH3-H include a direct memory access (DMA) controller (DMAC) that executes and controls DMA transfer.
PAGE 1233
V850ES/JG3-H, V850ES/JH3-H CHAPTER 22 DMA FUNCTION (DMA CONTROLLER) 22.
PAGE 1234
V850ES/JG3-H, V850ES/JH3-H CHAPTER 22 DMA FUNCTION (DMA CONTROLLER) 22.3 Registers (1) DMA source address registers 0 to 3 (DSA0 to DSA3) The DSA0 to DSA3 registers set the DMA source addresses (26 bits each) for DMA channel n (n = 0 to 3). These registers are divided into two 16-bit registers, DSAnH and DSAnL. These registers can be read or written in 16-bit units.
PAGE 1235
V850ES/JG3-H, V850ES/JH3-H CHAPTER 22 DMA FUNCTION (DMA CONTROLLER) (2) DMA destination address registers 0 to 3 (DDA0 to DDA3) The DDA0 to DDA3 registers set the DMA destination address (26 bits each) for DMA channel n (n = 0 to 3). These registers are divided into two 16-bit registers, DDAnH and DDAnL. These registers can be read or written in 16-bit units.
PAGE 1236
V850ES/JG3-H, V850ES/JH3-H CHAPTER 22 DMA FUNCTION (DMA CONTROLLER) (3) DMA transfer count registers 0 to 3 (DBC0 to DBC3) The DBC0 to DBC3 registers are 16-bit registers that set the transfer count for DMA channel n (n = 0 to 3). These registers hold the remaining transfer count during DMA transfer. These registers are decremented by 1 per transfer regardless of the transfer data unit (8/16 bits), and the transfer is terminated if a borrow occurs. These registers can be read or written in 16-bit units.
PAGE 1237
V850ES/JG3-H, V850ES/JH3-H CHAPTER 22 DMA FUNCTION (DMA CONTROLLER) (4) DMA addressing control registers 0 to 3 (DADC0 to DADC3) The DADC0 to DADC3 registers are 16-bit registers that control the DMA transfer mode for DMA channel n (n = 0 to 3). These registers can be read or written in 16-bit units. Reset sets these registers to 0000H.
PAGE 1238
V850ES/JG3-H, V850ES/JH3-H CHAPTER 22 DMA FUNCTION (DMA CONTROLLER) (5) DMA channel control registers 0 to 3 (DCHC0 to DCHC3) The DCHC0 to DCHC3 registers are 8-bit registers that control the DMA transfer operating mode for DMA channel n. These registers can be read or written in 8-bit or 1-bit units. (However, bit 7 is read-only and bits 1 and 2 are writeonly. If bit 1 or 2 is read, the read value is always 0.) Reset sets these registers to 00H.
PAGE 1239
V850ES/JG3-H, V850ES/JH3-H CHAPTER 22 DMA FUNCTION (DMA CONTROLLER) (6) DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3) The DTFR0 to DTFR3 registers are 8-bit registers that control the DMA transfer start trigger via interrupt request signals from on-chip peripheral I/O. The interrupt request signals set by these registers serve as DMA transfer start factors. These registers can be read or written in 8-bit units. However, DFn bit can be read or written in 1-bit units.
PAGE 1240
V850ES/JG3-H, V850ES/JH3-H CHAPTER 22 DMA FUNCTION (DMA CONTROLLER) Table 22-1.
PAGE 1241
V850ES/JG3-H, V850ES/JH3-H CHAPTER 22 DMA FUNCTION (DMA CONTROLLER) Table 22-1.
PAGE 1242
V850ES/JG3-H, V850ES/JH3-H CHAPTER 22 DMA FUNCTION (DMA CONTROLLER) (7) External DMA request enable register (EXDRQEN) The EXDRQEN register sets the DMA request to each DMA channel when connecting the external USB device by using the UDMARQm/UDMAAKm pin (m = 0, 1). This register can be read or written in 8-bit units. Reset sets This register to 00H.
PAGE 1243
V850ES/JG3-H, V850ES/JH3-H CHAPTER 22 DMA FUNCTION (DMA CONTROLLER) 22.4 Transfer Targets Table 22-2 shows the relationship between the transfer targets (√: Transfer enabled, ×: Transfer disabled). Table 22-2.
PAGE 1244
V850ES/JG3-H, V850ES/JH3-H CHAPTER 22 DMA FUNCTION (DMA CONTROLLER) 22.6 Transfer Types As a transfer type, the 2-cycle transfer is supported. In two-cycle transfer, data transfer is performed in two cycles, a read cycle and a write cycle. In the read cycle, the transfer source address is output and reading is performed from the source to the DMAC. In the write cycle, the transfer destination address is output and writing is performed from the DMAC to the destination.
PAGE 1245
V850ES/JG3-H, V850ES/JH3-H CHAPTER 22 DMA FUNCTION (DMA CONTROLLER) 22.7 DMA Channel Priorities The DMA channel priorities are fixed as follows. DMA channel 0 > DMA channel 1 > DMA channel 2 > DMA channel 3 The priorities are checked for every transfer cycle. 22.8 Time Related to DMA Transfer The time required to respond to a DMA request, and the minimum number of clocks required for DMA transfer are shown below.
PAGE 1246
V850ES/JG3-H, V850ES/JH3-H CHAPTER 22 DMA FUNCTION (DMA CONTROLLER) 22.9 DMA Transfer Start Factors There are two types of DMA transfer start factors, as shown below. (1) Request by software If the STGn bit is set to 1 while the DCHCn.TCn bit = 1 and Enn bit = 1 (DMA transfer enabled), DMA transfer is started.
PAGE 1247
V850ES/JG3-H, V850ES/JH3-H CHAPTER 22 DMA FUNCTION (DMA CONTROLLER) 22.10 DMA Abort Factors DMA transfer is aborted if a bus hold occurs. The same applies if transfer is executed between the internal memory/on-chip peripheral I/O and internal memory/onchip peripheral I/O. When the bus hold is cleared, DMA transfer is resumed. 22.11 End of DMA Transfer When DMA transfer has been completed the number of times set to the DBCn register and when the DCHCn.
PAGE 1248
V850ES/JG3-H, V850ES/JH3-H R01UH0042EJ0500 Rev.5.00 Aug 12, 2011 Figure 22-1. Priority of DMA (1) System clock DMA0 transfer request DMA1 transfer request DMA2 transfer request DF0 bit DF1 bit DF2 bit Preparation for transfer Read Write End processing Preparation for transfer Read Idle Mode of processing CPU processing DMA0 processing Write End processing Preparation for transfer Read Idle CPU processing Remarks 1. Transfer in the order of DMA0 → DMA1 → DMA2 2.
PAGE 1249
V850ES/JG3-H, V850ES/JH3-H R01UH0042EJ0500 Rev.5.00 Aug 12, 2011 Figure 22-2. Priority of DMA (2) System clock DMA0 transfer request DMA1 transfer request DMA2 transfer request DF0 bit DF1 bit DF2 bit Preparation for transfer Read Write End processing Preparation for transfer Idle Mode of processing CPU processing DMA0 processing Read Write End processing Preparation for transfer Read Idle CPU processing Remarks 1. Transfer in the order of DMA0 → DMA1 → DMA0 (DMA2 is held pending.) 2.
PAGE 1250
V850ES/JG3-H, V850ES/JH3-H CHAPTER 22 DMA FUNCTION (DMA CONTROLLER) Figure 22-3. Period in Which DMA Transfer Request Is Ignored (1) System clock DMAn transfer requestNote 1 DFn bit Mode of processing Note 2 CPU processing DMA transfer Preparation for transfer Note 2 Note 2 DMA0 processing Read cycle Write cycle CPU processing End processing Idle Transfer request generated after this can be acknowledged Notes 1. Interrupt from on-chip peripheral I/O, or software trigger (STGn bit) 2.
PAGE 1251
V850ES/JG3-H, V850ES/JH3-H R01UH0042EJ0500 Rev.5.00 Aug 12, 2011 Figure 22-4.
PAGE 1252
V850ES/JG3-H, V850ES/JH3-H CHAPTER 22 DMA FUNCTION (DMA CONTROLLER) 22.13 Cautions (1) Caution for VSWC register When using the DMAC, be sure to set an appropriate value, in accordance with the operating frequency, to the VSWC register. When the default value (77H) of the VSWC register is used, or if an inappropriate value is set to the VSWC register, the operation is not correctly performed (for details of the VSWC register, see 3.4.9 (1) (a) System wait control register (VSWC)).
PAGE 1253
V850ES/JG3-H, V850ES/JH3-H CHAPTER 22 DMA FUNCTION (DMA CONTROLLER) (b) Repeatedly execute setting INITn bit until transfer is forcibly terminated correctly <1> Suppress a request from the DMA request source of the channel to be forcibly terminated (stop operation of the on-chip peripheral I/O). <2> Check that the DMA transfer request of the channel to be forcibly terminated is not held pending, by using the DTFRn.DFn bit.
PAGE 1254
V850ES/JG3-H, V850ES/JH3-H CHAPTER 22 DMA FUNCTION (DMA CONTROLLER) (5) Memory boundary The operation is not guaranteed if the address of the transfer source or destination exceeds the area of the DMA target (external memory, internal RAM, or on-chip peripheral I/O) during DMA transfer. (6) Transferring misaligned data DMA transfer of misaligned data with a 16-bit bus width is not supported.
PAGE 1255
V850ES/JG3-H, V850ES/JH3-H CHAPTER 22 DMA FUNCTION (DMA CONTROLLER) (11) Read values of DSAn and DDAn registers Values in the middle of updating may be read from the DSAn and DDAn registers during DMA transfer (n = 0 to 3). For example, if the DSAnH register and then the DSAnL register are read when the DMA transfer source address (DSAn register) is 0000FFFFH and the count direction is incremental (DADCn.SAD1 and DADCn.
PAGE 1256
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION The V850ES/JG3-H and V850ES/JH3-H are provided with a dedicated interrupt controller (INTC) for interrupt servicing and can process a total of 86 to 93 interrupt requests. An interrupt is an event that occurs independently of program execution, and an exception is an event whose occurrence is dependent on program execution.
PAGE 1257
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 23-2.
PAGE 1258
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 23-2.
PAGE 1259
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 23-2.
PAGE 1260
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 23-2.
PAGE 1261
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION Remarks 1. Default Priority: The priority order when two or more maskable interrupt requests occur at the same time. The highest priority is 0. The priority order of non-maskable interrupt is INTWDT2 > NMI. Restored PC: The value of the program counter (PC) saved to EIPC, FEPC, or DBPC when interrupt servicing is started.
PAGE 1262
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 23-3.
PAGE 1263
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 23-3.
PAGE 1264
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 23-3.
PAGE 1265
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 23-3.
PAGE 1266
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION Remarks 1. Default Priority: The priority order when two or more maskable interrupt requests occur at the same time. The highest priority is 0. The priority order of non-maskable interrupt is INTWDT2 > NMI. Restored PC: The value of the program counter (PC) saved to EIPC, FEPC, or DBPC when interrupt servicing is started.
PAGE 1267
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION 23.2 Non-Maskable Interrupts A non-maskable interrupt request signal is acknowledged unconditionally, even when interrupts are in the interrupt disabled (DI) status. An NMI is not subject to priority control and takes precedence over all the other interrupt request signals. This product has the following two non-maskable interrupt request signals.
PAGE 1268
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 23-1.
PAGE 1269
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION 23.2.1 Operation If a non-maskable interrupt request signal is generated, the CPU performs the following processing, and transfers control to the handler routine. <1> Saves the restored PC to FEPC. <2> Saves the current PSW to FEPSW. <3> Writes exception code (0010H, 0020H) to the higher halfword (FECC) of ECR. <4> Sets the PSW.NP and PSW.ID bits to 1 and clears the PSW.EP bit to 0.
PAGE 1270
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION 23.2.2 Restore (1) From NMI pin input Execution is restored from the NMI servicing by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. <1> Loads the restored PC and PSW from FEPC and FEPSW, respectively, because the PSW.EP bit is 0 and the PSW.NP bit is 1.
PAGE 1271
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) From INTWDT2 signal Restoring from non-maskable interrupt servicing executed by the non-maskable interrupt request (INTWDT2) by using the RETI instruction is disabled. Execute the following software reset processing. Figure 23-4. Software Reset Processing INTWDT2 occurs.
PAGE 1272
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION 23.3 Maskable Interrupts Maskable interrupt request signals can be masked by interrupt control registers. The V850ES/JG3-H and V850ES/JH3-H have 84 to 91 maskable interrupt sources. If two or more maskable interrupt request signals are generated at the same time, they are acknowledged according to the default priority.
PAGE 1273
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 23-5.
PAGE 1274
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION 23.3.2 Restore Recovery from maskable interrupt servicing is carried out by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. <1> Loads the restored PC and PSW from EIPC and EIPSW because the PSW.EP bit is 0 and the PSW.NP bit is 0. <2> Transfers control back to the address of the restored PC and PSW.
PAGE 1275
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION 23.3.3 Priorities of maskable interrupts The INTC performs multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels.
PAGE 1276
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 23-7. Example of Processing in Which Another Interrupt Request Signal Is Issued While an Interrupt Is Being Serviced (1/2) Main routine Servicing of a EI Servicing of b EI Interrupt request b (level 2) Interrupt request a (level 3) Interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are enabled.
PAGE 1277
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 23-7. Example of Processing in Which Another Interrupt Request Signal Is Issued While an Interrupt Is Being Serviced (2/2) Main routine Servicing of i EI Interrupt request i (level 2) Servicing of k EI Interrupt request j (level 3) Interrupt request k (level 1) Interrupt request j is held pending because its priority is lower than that of i. k that occurs after j is acknowledged because it has the higher priority.
PAGE 1278
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 23-8. Example of Servicing Interrupt Request Signals Simultaneously Generated Main routine EI Interrupt request a (level 2) Interrupt request b (level 1) Interrupt request c (level 1) Default priority a>b>c Servicing of interrupt request b Servicing of interrupt request c . . Interrupt request b and c are acknowledged first according to their priorities.
PAGE 1279
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION 23.3.4 Interrupt control register (xxICn) The xxICn register is assigned to each interrupt request signal (maskable interrupt) and sets the control conditions for each maskable interrupt request. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 47H. Caution Disable interrupts (DI) or mask the interrupt to read the xxICn.xxIFn bit.
PAGE 1280
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 23-4.
PAGE 1281
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 23-4.
PAGE 1282
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 23-4.
PAGE 1283
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION 23.3.5 Interrupt mask registers 0 to 5 (IMR0 to IMR5) The IMR0 to IMR5 registers set the interrupt mask state for the maskable interrupts. The xxMKn bit of the IMR0 to IMR5 registers is equivalent to the xxICn.xxMKn bit. The IMRm register can be read or written in 16-bit units.
PAGE 1284
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2/2) After reset: FFFFH 15 R/W 14 Address: IMR2 FFFFF104H, IMR2L FFFFF104H, IMR2H FFFFF105H 12 13 11 10 9 8 IMR2 (IMR2HNote 1) TAA4CCMK0 TAA4OVMK TAA3CCMK1 TAA3CCMK0 TAA3OVMK TAA2CCMK1 TAA2CCMK0 TAA2OVMK 7 6 After reset: FFFFH 15 IMR1 (IMR1H 4 3 2 1 0 TAA1CCMK1 TAA1CCMK0 TAA1OVMK TAA0CCMK1 TAA0CCMK0 TAA0OVMK TMTIECMK TMT0CCMK1 IMR2L Note 1 5 R/W 14 Address: IMR1 FFFFF102H, IMR1L FFFFF102H, IMR1H FFFFF103H
PAGE 1285
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION 23.3.6 In-service priority register (ISPR) The ISPR register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt request signal is acknowledged, the bit of this register corresponding to the priority level of that interrupt request signal is set to 1 and remains set while the interrupt is serviced.
PAGE 1286
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION 23.3.7 ID flag This flag controls the maskable interrupt’s operating state, and stores control information regarding enabling or disabling of interrupt request signals. An interrupt disable flag (ID) is assigned to the PSW. Reset sets this flag to 00000020H.
PAGE 1287
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION 23.4 Software Exception A software exception is generated when the CPU executes the TRAP instruction, and can always be acknowledged. 23.4.1 Operation If a software exception occurs, the CPU performs the following processing, and transfers control to the handler routine. <1> Saves the restored PC to EIPC. <2> Saves the current PSW to EIPSW. <3> Writes an exception code to the lower 16 bits (EICC) of ECR (interrupt source).
PAGE 1288
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION 23.4.2 Restore Restoration from software exception processing is carried out by the RETI instruction. By executing the RETI instruction, the CPU carries out the following processing and shifts control to the restored PC’s address. <1> Loads the restored PC and PSW from EIPC and EIPSW because the PSW.EP bit is 1. <2> Transfers control to the address of the restored PC and PSW.
PAGE 1289
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION 23.4.3 EP flag The EP flag is a status flag used to indicate that exception processing is in progress. It is set when an exception occurs. After reset: 00000020H PSW 0 EP NP ID SAT CY OV S Z Exception processing status 0 Exception processing not in progress. 1 Exception processing in progress. R01UH0042EJ0500 Rev.5.
PAGE 1290
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION 23.5 Exception Trap An exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. In the V850ES/JG3-H and V850ES/JH3-H, an illegal opcode exception (ILGOP: Illegal Opcode Trap) is considered as an exception trap. 23.5.
PAGE 1291
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 23-11. Exception Trap Processing Exception trap (ILGOP) occurs CPU processing DBPC DBPSW PSW.NP PSW.EP PSW.ID PC Restored PC PSW 1 1 1 00000060H Exception processing (2) Restoration Restoration from an exception trap is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored PC.
PAGE 1292
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION 23.5.2 Debug trap A debug trap is an exception that is generated when the DBTRAP instruction is executed and is always acknowledged. (1) Operation Upon occurrence of a debug trap, the CPU performs the following processing. <1> Saves restored PC to DBPC. <2> Saves current PSW to DBPSW. <3> Sets the PSW.NP, PSW.EP, and PSW.ID bits to 1. <4> Sets handler address (00000060H) for debug trap to PC and transfers control.
PAGE 1293
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) Restoration Restoration from a debug trap is executed with the DBRET instruction. With the DBRET instruction, the CPU performs the following steps and transfers control to the address of the restored PC. <1> The restored PC and PSW are read from DBPC and DBPSW. <2> Control is transferred to the fetched address of the restored PC and PSW.
PAGE 1294
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION 23.6 External Interrupt Request Input Pins (NMI and INTP00 to INTP18) 23.6.1 Noise elimination (1) Eliminating noise on NMI pin The NMI pin has an internal noise elimination circuit that uses analog delay. Therefore, the input level of the NMI pin is not detected as an edge unless it is maintained for a specific time or longer. Therefore, an edge is detected after specific time. The NMI pin can be used to release the STOP mode.
PAGE 1295
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION (1) External interrupt falling, rising edge specification register 0 (INTF0, INTR0) The INTF0 and INTR0 registers are 8-bit registers that specify detection of the falling and rising edges of the NMI pin via bit 2 and the external interrupt pins (INTP00 to INTP04) via bits 0, 1, 3 to 5. These registers can be read or written in 8-bit or 1-bit units. Reset sets these registers to 00H.
PAGE 1296
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) External interrupt falling, rising edge specification register 2 (INTF2, INTR2) (V850ES/JH3-H only) The INTF2 and INTR2 registers are 8-bit registers that specify detection of the falling and rising edges of the external interrupt pins (INTP05 to INTP06). These registers can be read or written in 8-bit or 1-bit units. Reset sets these registers to 00H.
PAGE 1297
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION (3) External interrupt falling, rising edge specification register 3 (INTF3, INTR3) The INTF3 and INTR3 registers are 8-bit registers that specify detection of the falling and rising edges of the external interrupt pin (INTP07 to INTP09). These registers can be read or written in 8-bit or 1-bit units. Reset sets these registers to 00H.
PAGE 1298
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION (4) External interrupt falling, rising edge specification registers 4 (INTF4, INTR4) The INTF4 and INTR4 registers are 8-bit registers that specify detection of the falling and rising edges of the external interrupt pin (INTP10). These registers can be read or written in 8-bit or 1-bit units. Reset sets these registers to 00H.
PAGE 1299
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION (5) External interrupt falling, rising edge specification registers 5 (INTF5, INTR5) (V850ES/JG3-H only) The INTF5 and INTR5 registers are 8-bit registers that specify detection of the falling and rising edges of the external interrupt pin (INTP05). These registers can be read or written in 8-bit or 1-bit units. Reset sets these registers to 00H.
PAGE 1300
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION (6) External interrupt falling, rising edge specification register 9H (INTF9H, INTR9H) The INTF9H and INTR9H registers are 16-bit or 8-bit registers that specify detection of the falling and rising edges of the external interrupt pins (INTP11 to INTP18). These registers can be read or written in 8-bit or 1-bit units. Reset sets these registers to 0000H/00H.
PAGE 1301
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION (7) Noise elimination control register (INTNFC) Analog noise elimination and digital noise elimination can be selected for the INTP02 pin. The noise elimination settings are performed using the INTNFC register. When analog noise elimination is selected, the input level of the pin is detected as an edge by maintaining it for a specific time or longer.
PAGE 1302
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION 23.7 Interrupt Acknowledge Time of CPU Except the following cases, the interrupt acknowledge time of the CPU is 4 clocks minimum. To input interrupt request signals successively, input the next interrupt request signal at least 5 clocks after the preceding interrupt. • In IDLE1/IDLE2/STOP mode • When the external bus is accessed • When interrupt request non-sampling instructions are successively executed (see 23.
PAGE 1303
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION 23.8 Periods in Which Interrupts Are Not Acknowledged by CPU An interrupt is acknowledged by the CPU while an instruction is being executed. However, no interrupt will be acknowledged between an interrupt request non-sample instruction and the next instruction (interrupt is held pending). The interrupt request non-sample instructions are as follows.
PAGE 1304
V850ES/JG3-H, V850ES/JH3-H CHAPTER 24 KEY INTERRUPT FUNCTION CHAPTER 24 KEY INTERRUPT FUNCTION 24.1 Function A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the eight key input pins (KR0 to KR7) by setting the KRM register. Table 24-1.
PAGE 1305
V850ES/JG3-H, V850ES/JH3-H CHAPTER 24 KEY INTERRUPT FUNCTION 24.2 Register (1) Key return mode register (KRM) The KRM register controls the KRM0 to KRM7 bits using the KR0 to KR7 signals. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
PAGE 1306
V850ES/JG3-H, V850ES/JH3-H CHAPTER 25 STANDBY FUNCTION CHAPTER 25 STANDBY FUNCTION 25.1 Overview The power consumption of the system can be effectively reduced by using the standby modes in combination and selecting the appropriate mode for the application. The available standby modes are listed in Table 25-1. Table 25-1.
PAGE 1307
V850ES/JG3-H, V850ES/JH3-H CHAPTER 25 STANDBY FUNCTION Figure 25-1.
PAGE 1308
V850ES/JG3-H, V850ES/JH3-H CHAPTER 25 STANDBY FUNCTION 25.2 Registers (1) Power save control register (PSC) The PSC register is an 8-bit register that controls the standby function. The STP bit of this register is used to specify the standby mode. This register is a special register that can be written only by the special sequence combinations (see 3.4.8 Special registers). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
PAGE 1309
V850ES/JG3-H, V850ES/JH3-H CHAPTER 25 STANDBY FUNCTION (2) Power save mode register (PSMR) The PSMR register is an 8-bit register that controls the operation status in the power save mode and the clock operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
PAGE 1310
V850ES/JG3-H, V850ES/JH3-H CHAPTER 25 STANDBY FUNCTION (3) Oscillation stabilization time select register (OSTS) The wait time until the oscillation stabilizes after the STOP mode is released or the wait time until the on-chip flash memory stabilizes after the IDLE2 mode is released is controlled by the OSTS register. This register can be read or written in 8-bit units. Reset sets this register to 06H.
PAGE 1311
V850ES/JG3-H, V850ES/JH3-H CHAPTER 25 STANDBY FUNCTION 25.3 HALT Mode 25.3.1 Setting and operation status The HALT mode is set when a dedicated instruction (HALT) is executed in the normal operation mode. In the HALT mode, the clock oscillator continues operating. Only clock supply to the CPU is stopped; clock supply to the other on-chip peripheral functions continues. As a result, program execution is stopped, and the internal RAM retains the contents before the HALT mode was set.
PAGE 1312
V850ES/JG3-H, V850ES/JH3-H CHAPTER 25 STANDBY FUNCTION (2) Releasing HALT mode by reset The same operation as the normal reset operation is performed. Table 25-3.
PAGE 1313
V850ES/JG3-H, V850ES/JH3-H CHAPTER 25 STANDBY FUNCTION 25.4 IDLE1 Mode 25.4.1 Setting and operation status The IDLE1 mode is set by setting the PSMR.PSM1 and PSMR.PSM0 bits to 00 and setting the PSC.STP bit to 1 in the normal operation mode. In the IDLE1 mode, the clock oscillator, PLL, and flash memory continue operating but clock supply to the CPU and other on-chip peripheral functions stops.
PAGE 1314
V850ES/JG3-H, V850ES/JH3-H CHAPTER 25 STANDBY FUNCTION 25.4.2 Releasing IDLE1 mode The IDLE1 mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal), unmasked external interrupt request signal (INTP00 to INTP18 pin input), unmasked internal interrupt request signal from a peripheral function operable in the IDLE1 mode, or reset signal (reset by RESET pin input, WDT2RES signal, low-voltage detector (LVI), or clock monitor (CLM)).
PAGE 1315
V850ES/JG3-H, V850ES/JH3-H CHAPTER 25 STANDBY FUNCTION Table 25-5.
PAGE 1316
V850ES/JG3-H, V850ES/JH3-H CHAPTER 25 STANDBY FUNCTION 25.5 IDLE2 Mode 25.5.1 Setting and operation status The IDLE2 mode is set by setting the PSMR.PSM1 and PSMR.PSM0 bits to 10 and setting the PSC.STP bit to 1 in the normal operation mode. In the IDLE2 mode, the clock oscillator continues operation but clock supply to the CPU, PLL, flash memory, and other on-chip peripheral functions stops.
PAGE 1317
V850ES/JG3-H, V850ES/JH3-H CHAPTER 25 STANDBY FUNCTION 25.5.2 Releasing IDLE2 mode The IDLE2 mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal), unmasked external interrupt request signal (INTP0 to INTP18 pin input), unmasked internal interrupt request signal from the peripheral functions operable in the IDLE2 mode, or reset signal (reset by RESET pin input, WDT2RES signal, low-voltage detector (LVI), or clock monitor (CLM)).
PAGE 1318
V850ES/JG3-H, V850ES/JH3-H CHAPTER 25 STANDBY FUNCTION Table 25-7.
PAGE 1319
V850ES/JG3-H, V850ES/JH3-H CHAPTER 25 STANDBY FUNCTION 25.5.3 Securing setup time when releasing IDLE2 mode Secure the setup time for the flash memory after releasing the IDLE2 mode because the operation of the blocks other than the main clock oscillator stops after the IDLE2 mode is set. (1) Releasing IDLE2 mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal Secure the specified setup time by setting the OSTS register.
PAGE 1320
V850ES/JG3-H, V850ES/JH3-H CHAPTER 25 STANDBY FUNCTION 25.6 STOP Mode 25.6.1 Setting and operation status The STOP mode is set by setting the PSMR.PSM1 and PSMR.PSM0 bits to 01 or 11 and setting the PSC.STP bit to 1 in the normal operation mode. In the STOP mode, the subclock oscillator continues operating but the main clock oscillator stops. Clock supply to the CPU and the on-chip peripheral functions is stopped.
PAGE 1321
V850ES/JG3-H, V850ES/JH3-H CHAPTER 25 STANDBY FUNCTION Table 25-8. Operation After Releasing STOP Mode by Interrupt Request Signal Release Source Interrupt Enabled (EI) Status Interrupt Disabled (DI) Status Non-maskable interrupt request signal Execution branches to the handler address after securing the oscillation stabilization time. Maskable interrupt request signal Execution branches to the handler address or the next instruction is executed after securing the oscillation stabilization time.
PAGE 1322
V850ES/JG3-H, V850ES/JH3-H CHAPTER 25 STANDBY FUNCTION Table 25-9.
PAGE 1323
V850ES/JG3-H, V850ES/JH3-H CHAPTER 25 STANDBY FUNCTION 25.6.3 Securing oscillation stabilization time when releasing STOP mode Secure the oscillation stabilization time for the main clock oscillator after releasing the STOP mode because the operation of the main clock oscillator stops after STOP mode is set. (1) Releasing STOP mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal Secure the oscillation stabilization time by setting the OSTS register.
PAGE 1324
V850ES/JG3-H, V850ES/JH3-H CHAPTER 25 STANDBY FUNCTION 25.7 Subclock Operation Mode 25.7.1 Setting and operation status The subclock operation mode is set by setting the PCC.CK3 bit to 1 in the normal operation mode. When the subclock operation mode is set, the internal system clock is changed from the main clock to the subclock. Check whether the clock has been switched by using the PCC.CLS bit. When the PCC.MCK bit is set to 1, the operation of the main clock oscillator is stopped.
PAGE 1325
V850ES/JG3-H, V850ES/JH3-H CHAPTER 25 STANDBY FUNCTION Table 25-10.
PAGE 1326
V850ES/JG3-H, V850ES/JH3-H CHAPTER 25 STANDBY FUNCTION 25.8 Sub-IDLE Mode 25.8.1 Setting and operation status The sub-IDLE mode is set by setting the PSMR.PSM1 and PSMR.PSM0 bits to 00 or 10 and setting the PSC.STP bit to 1 in the subclock operation mode. In this mode, the clock oscillator continues operating but clock supply to the CPU, flash memory, and the other on-chip peripheral functions is stopped.
PAGE 1327
V850ES/JG3-H, V850ES/JH3-H CHAPTER 25 STANDBY FUNCTION Table 25-11. Operation After Releasing Sub-IDLE Mode by Interrupt Request Signal Release Source Interrupt Enabled (EI) Status Non-maskable interrupt request Interrupt Disabled (DI) Status Execution branches to the handler address. signal Maskable interrupt request signal Execution branches to the handler address The next instruction is executed. or the next instruction is executed.
PAGE 1328
V850ES/JG3-H, V850ES/JH3-H CHAPTER 26 RESET FUNCTIONS CHAPTER 26 RESET FUNCTIONS 26.1 Overview The following reset functions are available.
PAGE 1329
V850ES/JG3-H, V850ES/JH3-H CHAPTER 26 RESET FUNCTIONS 26.2 Registers to Check Reset Source The V850ES/JG3-H and V850ES/JH3-H have four kinds of reset sources. After a reset has been released, the source of the reset that occurred can be checked with the reset source flag register (RESF). (1) Reset source flag register (RESF) The RESF register is a special register that can be written only by a combination of specific sequences (see 3.4.8 Special registers).
PAGE 1330
V850ES/JG3-H, V850ES/JH3-H CHAPTER 26 RESET FUNCTIONS 26.3 Operation 26.3.1 Reset operation via RESET pin When a low level is input to the RESET pin, the system is reset, and each hardware unit is initialized. When the level of the RESET pin is changed from low to high, the reset status is released. Table 26-1.
PAGE 1331
V850ES/JG3-H, V850ES/JH3-H CHAPTER 26 RESET FUNCTIONS Figure 26-2. Timing of Reset Operation by RESET Pin Input fX fCLK Initialized to fXX/8 operation RESET Analog delay Analog delay Analog delay Analog delay (eliminated as noise) (eliminated as noise) Internal system reset signal Counting of oscillation stabilization time Oscillation stabilization timer overflows Figure 26-3.
PAGE 1332
V850ES/JG3-H, V850ES/JH3-H CHAPTER 26 RESET FUNCTIONS 26.3.2 Reset operation by watchdog timer 2 When watchdog timer 2 is set to the reset operation mode due to overflow, upon watchdog timer 2 overflow (WDT2RES signal generation), a system reset is executed and the hardware is initialized to the initial status. Following watchdog timer 2 overflow, the reset status is entered and lasts the predetermined time (analog delay), and the reset status is then automatically released.
PAGE 1333
V850ES/JG3-H, V850ES/JH3-H CHAPTER 26 RESET FUNCTIONS Figure 26-4. Timing of Reset Operation by WDT2RES Signal Generation fX fCLK Initialized to fXX/8 operation WDT2RES Analog delay Internal system reset signal Counting of oscillation stabilization time Oscillation stabilization timer overflow R01UH0042EJ0500 Rev.5.
PAGE 1334
V850ES/JG3-H, V850ES/JH3-H CHAPTER 26 RESET FUNCTIONS 26.3.3 Reset operation by low-voltage detector If the supply voltage falls below the voltage detected by the low-voltage detector when LVI operation is enabled, a system reset is executed (when the LVIM.LVIMD bit is set to 1), and the hardware is initialized to the initial status. The reset status lasts from when a supply voltage drop has been detected until the supply voltage rises above the LVI detection voltage.
PAGE 1335
V850ES/JG3-H, V850ES/JH3-H CHAPTER 26 RESET FUNCTIONS 26.3.4 Operation after reset release After the reset is released, the main clock starts oscillation and oscillation stabilization time (OSTS register initial value: 216/fX) is secured, and the CPU starts program execution. WDT2 immediately begins to operate after a reset has been released using the internal oscillation clock as a source clock. Figure 26-5.
PAGE 1336
V850ES/JG3-H, V850ES/JH3-H CHAPTER 26 RESET FUNCTIONS 26.3.5 Reset function operation flow Start (reset source occurs) Set RESF registerNote 1 Reset occurs → reset release Internal oscillation and main clock oscillation start, WDT2 count up starts (reset mode) Main clock oscillation stabilization time secured? No Yes (in normal operation mode) No WDT2 overflow? Yes (in emergent operation mode) fCPU = fRNote 2 CCLS.
PAGE 1337
V850ES/JG3-H, V850ES/JH3-H CHAPTER 27 CLOCK MONITOR CHAPTER 27 CLOCK MONITOR 27.1 Functions The clock monitor samples the main clock by using the internal oscillation clock and generates a reset request signal when oscillation of the main clock is stopped. Once the operation of the clock monitor has been enabled by an operation enable flag, it cannot be cleared to 0 by any means other than reset. When a reset by the clock monitor occurs, the RESF.CLMRF bit is set.
PAGE 1338
V850ES/JG3-H, V850ES/JH3-H CHAPTER 27 CLOCK MONITOR 27.3 Register The clock monitor is controlled by the clock monitor mode register (CLM). (1) Clock monitor mode register (CLM) The CLM register is a special register. This can be written only in a special combination of sequences (see 3.4.8 Special registers). This register is used to set the operation mode of the clock monitor. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
PAGE 1339
V850ES/JG3-H, V850ES/JH3-H CHAPTER 27 CLOCK MONITOR 27.4 Operation This section explains the functions of the clock monitor. The start and stop conditions are as follows. Enabling operation by setting the CLM.CLME bit to 1 • While oscillation stabilization time is being counted after STOP mode is released • When the main clock is stopped (from when PCC.MCK bit = 1 during subclock operation to when PCC.
PAGE 1340
V850ES/JG3-H, V850ES/JH3-H CHAPTER 27 CLOCK MONITOR (1) Operation when main clock oscillation is stopped (CLME bit = 1) If oscillation of the main clock is stopped when the CLME bit = 1, an internal reset signal is generated as shown in Figure 27-2. Figure 27-2. Reset Period Due to That Oscillation of Main Clock Is Stopped Four internal oscillation clocks Main clock Internal oscillation clock Internal reset signal CLM.CLME bit RESF.
PAGE 1341
V850ES/JG3-H, V850ES/JH3-H CHAPTER 27 CLOCK MONITOR (3) Operation in STOP mode or after STOP mode is released If the STOP mode is set with the CLM.CLME bit = 1, the monitor operation is stopped in the STOP mode and while the oscillation stabilization time is being counted. After the oscillation stabilization time, the monitor operation is automatically started. Figure 27-4.
PAGE 1342
V850ES/JG3-H, V850ES/JH3-H CHAPTER 28 LOW-VOLTAGE DETECTOR (LVI) CHAPTER 28 LOW-VOLTAGE DETECTOR (LVI) 28.1 Functions The low-voltage detector (LVI) has the following functions. • If the interrupt occurrence at low voltage detection is selected, the low-voltage detector continuously compares the supply voltage (VDD) and the detected voltage (VLVI), and generates an internal interrupt signal when the supply voltage drops or rises across the detected voltage.
PAGE 1343
V850ES/JG3-H, V850ES/JH3-H CHAPTER 28 LOW-VOLTAGE DETECTOR (LVI) 28.3 Registers The low-voltage detector is controlled by the following registers. • Low-voltage detection register (LVIM) • Internal RAM data status register (RAMS) (1) Low-voltage detection register (LVIM) The LVIM register is a special register. This can be written only in the special combination of the sequences (see 3.4.8 Special registers).
PAGE 1344
V850ES/JG3-H, V850ES/JH3-H CHAPTER 28 LOW-VOLTAGE DETECTOR (LVI) (2) Internal RAM data status register (RAMS) The RAMS register is a special register. This can be written only in a special combination of sequences (see 3.4.8 Special registers). This register is a flag register that indicates whether the internal RAM is valid or not. This register can be read or written in 8-bit or 1-bit units. The set/clear conditions for the RAMF bit are shown below.
PAGE 1345
V850ES/JG3-H, V850ES/JH3-H CHAPTER 28 LOW-VOLTAGE DETECTOR (LVI) 28.4 Operation Depending on the setting of the LVIM.VIMD bit, an interrupt signal (INTLVI) or an internal reset signal is generated. How to specify each operation is described below, together with timing charts. 28.4.1 To use for internal reset signal <1> Mask the interrupt of LVI. <2> Set the LVIM.LVION bit to 1 (to enable operation). <3> Insert a wait cycle of 0.2 ms (max.) or more by software. <4> By using the LVIM.
PAGE 1346
V850ES/JG3-H, V850ES/JH3-H CHAPTER 28 LOW-VOLTAGE DETECTOR (LVI) 28.4.2 To use for interrupt <1> Mask the interrupt of LVI. <2> Set the LVIM.LVION bit to 1 (to enable operation). <3> Insert a wait cycle of 0.2 ms (max.) or more by software. <4> By using the LVIM.LVIF bit, check if the supply voltage > detected voltage. <5> Clear the interrupt request flag of LVI. <6> Unmask the interrupt of LVI. Clear the LVION bit to 0. Figure 28-3.
PAGE 1347
V850ES/JG3-H, V850ES/JH3-H CHAPTER 28 LOW-VOLTAGE DETECTOR (LVI) 28.5 RAM Retention Voltage Detection Operation The supply voltage and detected voltage are compared. When the supply voltage drops below the detected voltage (including on power application), the RAMS.RAMF bit is set to 1. Figure 28-4. Operation Timing of RAM Retention Voltage Detection Function Initialize RAM (RAMF bit is also cleared) VDD < 2.0 V detected Set RAMF bit Initialize RAM (RAMF bit is also cleared) Supply voltage (VDD) 2.
PAGE 1348
V850ES/JG3-H, V850ES/JH3-H CHAPTER 29 CRC FUNCTION CHAPTER 29 CRC FUNCTION 29.1 Functions • CRC operation circuit for detection of data block errors • Generation of 16-bit CRC code using a CRC-CCITT (X16 + X12 + X5 + 1) generation polynomial for blocks of data of any length in 8-bit units • CRC code is set to the CRCD data register each time 1-byte data is transferred to the CRCIN register, after the initial value is set to the CRCD register. 29.
PAGE 1349
V850ES/JG3-H, V850ES/JH3-H CHAPTER 29 CRC FUNCTION 29.3 Registers (1) CRC input register (CRCIN) The CRCIN register is an 8-bit register for setting data. This register can be read or written in 8-bit units. Reset sets this register to 00H. After reset: 00H R/W Address: FFFFF310H 6 7 5 4 3 2 1 0 CRCIN (2) CRC data register (CRCD) The CRCD register is a 16-bit register that stores the CRC-CCITT operation results. This register can be read or written in 16-bit units.
PAGE 1350
V850ES/JG3-H, V850ES/JH3-H CHAPTER 29 CRC FUNCTION 29.4 Operation An example of the CRC operation circuit is shown below. Figure 29-2. CRC Operation Circuit Operation Example (LSB First) b7 b0 (1) Setting of CRCIN = 01H b15 b0 (2) CRCD register read 1189H CRC code is stored The code when 01H is sent LSB first is (1000 0000).
PAGE 1351
V850ES/JG3-H, V850ES/JH3-H CHAPTER 29 CRC FUNCTION 29.5 Usage Method How to use the CRC logic circuit is described below. Figure 29-3. CRC Operation Flow Start Write of 0000H to CRCD register Input data exists? Yes No CRCD register read CRCIN register write End [Basic usage method] <1> Write 0000H to the CRCD register. <2> Write the required quantity of data to the CRCIN register. <3> Read the CRCD register. R01UH0042EJ0500 Rev.5.
PAGE 1352
V850ES/JG3-H, V850ES/JH3-H CHAPTER 29 CRC FUNCTION Communication errors can easily be detected if the CRC code is transmitted/received along with transmit/receive data when transmitting/receiving data consisting of several bytes. The following is an illustration using the transmission of 12345678H (0001 0010 0011 0100 0101 0110 0111 1000B) LSB-first as an example. Figure 29-4.
PAGE 1353
V850ES/JG3-H, V850ES/JH3-H CHAPTER 30 REGULATOR CHAPTER 30 REGULATOR 30.1 Overview The V850ES/JG3-H and V850ES/JH3-H include a regulator to reduce power consumption and noise. This regulator supplies a stepped-down VDD power supply voltage to the oscillator block and internal logic circuits (except the A/D converter, D/A converter, and output buffers). Figure 30-1.
PAGE 1354
V850ES/JG3-H, V850ES/JH3-H CHAPTER 30 REGULATOR 30.2 Operation The regulators of the V850ES/JG3-H and V850ES/JH3-H always operate in any mode (normal operation mode, HALT mode, IDLE1 mode, IDLE2 mode, STOP mode, subclock operation mode, sub IDLE mode, or during reset). Be sure to connect a capacitor (4.7 μF (recommended value)) to the REGC pinNote to stabilize the regulator output. A diagram of the regulator pin connection method is shown below. Note There are two REGC pins. Figure 30-2.
PAGE 1355
V850ES/JG3-H, V850ES/JH3-H CHAPTER 31 FLASH MEMORY CHAPTER 31 FLASH MEMORY The V850ES/JG3-H and V850ES/JH3-H incorporate a flash memory. • μPD70F3760, 70F3765, 70F3770, 70F3771: 256 KB flash memory • μPD70F3761, 70F3766: 384 KB flash memory • μPD70F3762, 70F3767: 512 KB flash memory Flash memory versions offer the following advantages for development environments and mass production applications. { For altering software after the V850ES/JG3-H and V850ES/JH3-H are soldered onto the target system.
PAGE 1356
V850ES/JG3-H, V850ES/JH3-H CHAPTER 31 FLASH MEMORY 31.2 Memory Configuration The internal flash memory area of the V850ES/JG3-H and V850ES/JH3-H is divided into 64, 96 or 128 blocks and can be programmed/erased in block units. All the blocks can also be erased at once. When the boot swap function is used, the physical memory located at the addresses of blocks 0 to 15 is replaced by the physical memory located at the addresses of blocks 16 to 31. For details of the boot swap function, see 31.
PAGE 1357
V850ES/JG3-H, V850ES/JH3-H CHAPTER 31 FLASH MEMORY 31.3 Functional Overview The internal flash memory of the V850ES/JG3-H and V850ES/JH3-H can be rewritten by using the rewrite function of the dedicated flash programmer, regardless of whether the V850ES/JG3-H and V850ES/JH3-H have already been mounted on the target system or not (off-board/on-board programming).
PAGE 1358
V850ES/JG3-H, V850ES/JH3-H CHAPTER 31 FLASH MEMORY Table 31-2. Basic Functions Function Functional Outline Support (√: Supported, ×: Not supported) On-Board/Off-Board Self Programming Programming Blank check The erasure status of the entire memory is √ √ checked. Chip erasure The contents of the entire memory area are × √ Note erased all at once. Block erasure The contents of specified memory blocks √ √ √ √ are erased.
PAGE 1359
V850ES/JG3-H, V850ES/JH3-H CHAPTER 31 FLASH MEMORY Table 31-4.
PAGE 1360
V850ES/JG3-H, V850ES/JH3-H CHAPTER 31 FLASH MEMORY 31.4 Rewriting by Dedicated Flash Programmer The flash memory can be rewritten by using a dedicated flash programmer after the V850ES/JG3-H and V850ES/JH3H are mounted on the target system (on-board programming). The flash memory can also be rewritten before the device is mounted on the target system (off-board programming) by using a dedicated program adapter (FA series). 31.4.
PAGE 1361
V850ES/JG3-H, V850ES/JH3-H CHAPTER 31 FLASH MEMORY 31.4.2 Communication mode Communication between the dedicated flash programmer and the V850ES/JG3-H or V850ES/JH3-H is performed by serial communication using the UARTC0, CSIF0, or CSIF3 interface of the V850ES/JG3-H or V850ES/JH3-H. (1) UARTC0 Transfer rate: 9,600 to 153,600 bps Figure 31-3.
PAGE 1362
V850ES/JG3-H, V850ES/JH3-H CHAPTER 31 FLASH MEMORY (3) CSIF0 + HS, CSIF3 + HS Serial clock: 5 MHz or less (MSB first) Figure 31-5. Communication with Dedicated Flash Programmer (CSIF0 + HS, CSIF3 + HS) FLMD0 FLMD0 FLMD1 FLMD1Note VDD VDD GND VSS RESET Dedicated flash programmer SI SO SCK HS RESET SOF0, SOF3 SIF0, SIF3 SCKF0, SCKF3 V850ES/JG3-H, V850ES/JH3-H P913 Note Connect the FLMD1 pin to the flash programmer or connect to GND via a pull-down resistor on the board.
PAGE 1363
V850ES/JG3-H, V850ES/JH3-H CHAPTER 31 FLASH MEMORY Table 31-5.
PAGE 1364
V850ES/JG3-H, V850ES/JH3-H CHAPTER 31 FLASH MEMORY Table 31-6. Wiring of V850ES/JG3-H Flash Writing Adapters (1/3) Pin No.
PAGE 1365
V850ES/JG3-H, V850ES/JH3-H CHAPTER 31 FLASH MEMORY Table 31-6. Wiring of V850ES/JG3-H Flash Writing Adapters (2/3) Pin No.
PAGE 1366
V850ES/JG3-H, V850ES/JH3-H CHAPTER 31 FLASH MEMORY Table 31-6. Wiring of V850ES/JG3-H Flash Writing Adapters (3/3) Pin No. Pin Name Recommended Connection 61 REGC Connect the REGC pin to GND via 4.
PAGE 1367
V850ES/JG3-H, V850ES/JH3-H CHAPTER 31 FLASH MEMORY Figure 31-6. Wiring Example of V850ES/JG3-H Flash Writing Adapter (In CSIF0 + HS Mode) (1/2) 4.7 μF 76 70 65 ND 75 G D N G D VD D VD 60 55 Note 2 51 50 Note 1 80 45 85 40 V850ES/JG3-H 90 35 95 Connect this pin to GND. 30 ot e 4 Connect this pin to VDD. N 100 Note 3 5 10 15 20 26 25 D N G D VD D N G 4.7 μ F 1 RFU-3 SI R01UH0042EJ0500 Rev.5.
PAGE 1368
V850ES/JG3-H, V850ES/JH3-H CHAPTER 31 FLASH MEMORY Figure 31-6. Wiring Example of V850ES/JG3-H Flash Writing Adapter (In CSIF0 + HS Mode) (2/2) Notes 1. Corresponding pins when CSIF3 is used. 2. Wire the FLMD1 pin as shown below, or connect it to GND on board via a pull-down resistor. 3. Create an oscillator on the flash writing adapter (shown in broken lines) and supply a clock. Here is an example of the oscillator. Example: X1 X2 4. Corresponding pins when UARTC0 is used.
PAGE 1369
V850ES/JG3-H, V850ES/JH3-H CHAPTER 31 FLASH MEMORY Table 31-7. Wiring of V850ES/JH3-H Flash Writing Adapters (1/4) Pin No.
PAGE 1370
V850ES/JG3-H, V850ES/JH3-H CHAPTER 31 FLASH MEMORY Table 31-7. Wiring of V850ES/JH3-H Flash Writing Adapters (2/4) Pin No.
PAGE 1371
V850ES/JG3-H, V850ES/JH3-H CHAPTER 31 FLASH MEMORY Table 31-7. Wiring of V850ES/JH3-H Flash Writing Adapters (3/4) Pin No.
PAGE 1372
V850ES/JG3-H, V850ES/JH3-H CHAPTER 31 FLASH MEMORY Table 31-7. Wiring of V850ES/JH3-H Flash Writing Adapters (4/4) Pin No.
PAGE 1373
V850ES/JG3-H, V850ES/JH3-H CHAPTER 31 FLASH MEMORY Figure 31-7. Wiring Example of V850ES/JH3-H Flash Writing Adapter (In CSIF0 + HS Mode) (1/2) D VD D N G D VD D N G 102 103 100 95 90 85 80 Note 2 75 70 65 Note 1 4.7 μF 64 105 60 110 55 115 V850ES/JH3-H 50 120 45 125 Connect this pin to GND. 4.7 μF Note 3 128 1 5 10 15 40 Connect this pin to VDD. 20 25 30 Note 4 39 35 38 G D N N D VD D G RFU-3 SI R01UH0042EJ0500 Rev.5.
PAGE 1374
V850ES/JG3-H, V850ES/JH3-H CHAPTER 31 FLASH MEMORY Figure 31-7. Wiring Example of V850ES/JH3-H Flash Writing Adapter (In CSIF0 + HS Mode) (2/2) Notes 1. Corresponding pins when CSIF3 is used. 2. Wire the FLMD1 pin as shown below, or connect it to GND on board via a pull-down resistor. 3. Create an oscillator on the flash writing adapter (shown in broken lines) and supply a clock. Here is an example of the oscillator. Example: X1 X2 4. Corresponding pins when UARTC0 is used.
PAGE 1375
V850ES/JG3-H, V850ES/JH3-H CHAPTER 31 FLASH MEMORY 31.4.3 Flash memory control The following shows the procedure for manipulating the flash memory. Figure 31-8. Procedure for Manipulating Flash Memory Start Switch to flash memory programming mode Supplies FLMD0 pulse Select communication system Manipulate flash memory End? No Yes End R01UH0042EJ0500 Rev.5.
PAGE 1376
V850ES/JG3-H, V850ES/JH3-H CHAPTER 31 FLASH MEMORY 31.4.4 Selection of communication mode In the V850ES/JG3-H and V850ES/JH3-H, the communication mode is selected by inputting pulses (12 pulses max.) to the FLMD0 pin after switching to the flash memory programming mode. The FLMD0 pulse is generated by the dedicated flash programmer. The following shows the relationship between the number of pulses and the communication mode. Figure 31-9.
PAGE 1377
V850ES/JG3-H, V850ES/JH3-H CHAPTER 31 FLASH MEMORY 31.4.5 Communication commands The V850ES/JG3-H and V850ES/JH3-H communicate with the dedicated flash programmer by means of commands. The signals sent from the dedicated flash programmer to the V850ES/JG3-H and V850ES/JH3-H are called “commands”. The response signals sent from the V850ES/JG3-H and V850ES/JH3-H to the dedicated flash programmer are called “response commands”. Figure 31-10.
PAGE 1378
V850ES/JG3-H, V850ES/JH3-H CHAPTER 31 FLASH MEMORY 31.4.6 Pin connection When performing on-board writing, mount a connector on the target system to connect to the dedicated flash programmer. Also, incorporate a function on-board to switch from the normal operation mode to the flash memory programming mode. In the flash memory programming mode, all the pins not used for flash memory programming become the same status as that immediately after reset.
PAGE 1379
V850ES/JG3-H, V850ES/JH3-H CHAPTER 31 FLASH MEMORY Table 31-9. Relationship Between FLMD0 and FLMD1 Pins and Operation Mode When Reset Is Released FLMD0 FLMD1 0 Don’t care VDD 0 VDD VDD Operation Mode Normal operation mode Flash memory programming mode Setting prohibited (3) Serial interface pin The following shows the pins used by each serial interface. Table 31-10.
PAGE 1380
V850ES/JG3-H, V850ES/JH3-H CHAPTER 31 FLASH MEMORY (b) Malfunction of other device When the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that is connected to another device (input), the signal is output to the other device, causing the device to malfunction. To avoid this, isolate the connection to the other device. Figure 31-14.
PAGE 1381
V850ES/JG3-H, V850ES/JH3-H CHAPTER 31 FLASH MEMORY (4) RESET pin When the reset signals of the dedicated flash programmer are connected to the RESET pin that is connected to the reset signal generator on-board, a conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the reset signal generator. When a reset signal is input from the user system in the flash memory programming mode, the programming operation will not be performed correctly.
PAGE 1382
V850ES/JG3-H, V850ES/JH3-H CHAPTER 31 FLASH MEMORY 31.5 Rewriting by Self Programming 31.5.1 Overview The V850ES/JG3-H and V850ES/JH3-H support a flash macro service that allows the user program to rewrite the internal flash memory by itself. By using this interface and a self programming library that is used to rewrite the flash memory with a user application program, the flash memory can be rewritten by a user application transferred in advance to the internal RAM or external memory.
PAGE 1383
V850ES/JG3-H, V850ES/JH3-H CHAPTER 31 FLASH MEMORY 31.5.2 Features (1) Secure self programming (boot swap function) The V850ES/JG3-H and V850ES/JH3-H support a boot swap function that can exchange the physical memory of blocks 0 to 15 with the physical memory of blocks 16 to 31.
PAGE 1384
V850ES/JG3-H, V850ES/JH3-H CHAPTER 31 FLASH MEMORY 31.5.3 Standard self programming flow The entire processing to rewrite the flash memory by flash self programming is illustrated below. Figure 31-18.
PAGE 1385
V850ES/JG3-H, V850ES/JH3-H CHAPTER 31 FLASH MEMORY 31.5.4 Flash functions Table 31-11.
PAGE 1386
V850ES/JG3-H, V850ES/JH3-H CHAPTER 31 FLASH MEMORY 31.5.6 Internal resources used The following table lists the internal resources used for self programming. These internal resources can also be used freely for purposes other than self programming. Table 31-12. Internal Resources Used Resource Name Description An extension of the stack used by the user is used by the library (can be used in both the Stack area internal RAM and external RAM).
PAGE 1387
V850ES/JG3-H, V850ES/JH3-H CHAPTER 31 FLASH MEMORY 31.6 Creating ROM code to place order for previously written product Before placing an order with Renesas Electronics for a previously written product, the ROM code for the order must be created. To create the ROM code, use the Hex Consolidation Utility (hereafter abbreviated to HCU) on the finished programs (hex files) and optional data (such as security settings for flash memory programs).
PAGE 1388
V850ES/JG3-H, V850ES/JH3-H CHAPTER 32 ON-CHIP DEBUG FUNCTION CHAPTER 32 ON-CHIP DEBUG FUNCTION The on-chip debug function of the V850ES/JG3-H and V850ES/JH3-H can be implemented by the following two methods. • Using the DCU (debug control unit) On-chip debug function is implemented by the on-chip DCU in the V850ES/JG3-H and V850ES/JH3-H, with using the DRST, DCK, DMS, DDI, and DDO pins as the debug interface pins.
PAGE 1389
V850ES/JG3-H, V850ES/JH3-H CHAPTER 32 ON-CHIP DEBUG FUNCTION 32.1 Debugging with DCU Programs can be debugged using the debug interface pins (DRST, DCK, DMS, DDI, and DDO) to connect the on-chip debug emulator (MINICUBE). 32.1.1 Connection circuit example Figure 32-1.
PAGE 1390
V850ES/JG3-H, V850ES/JH3-H CHAPTER 32 ON-CHIP DEBUG FUNCTION (2) DCK This is a clock input signal. It supplies a 20 MHz or 10 MHz clock from MINICUBE. In the on-chip debug unit, the DMS and DDI signals are sampled at the rising edge of the DCK signal, and the data DDO is output at its falling edge. (3) DMS This is a transfer mode select signal. The transfer status in the debug unit changes depending on the level of the DMS signal. (4) DDI This is a data input signal.
PAGE 1391
V850ES/JG3-H, V850ES/JH3-H CHAPTER 32 ON-CHIP DEBUG FUNCTION 32.1.3 Maskable functions Reset, NMI, INTWDT2, WAIT, and HLDRQ signals can be masked. The maskable functions with the debugger (ID850QB) and the corresponding V850ES/JG3-H and V850ES/JH3-H functions are listed below. Table 32-2.
PAGE 1392
V850ES/JG3-H, V850ES/JH3-H After reset: 01HNote CHAPTER 32 ON-CHIP DEBUG FUNCTION R/W Address: FFFFF9FCH < > OCDM 0 0 0 0 0 0 0 OCDM0 OCDM0 Operation mode 0 Selects normal operation mode (in which a pin that functions alternately as on-chip debug function pin is used as a port/peripheral function pin) and disconnects the on-chip pull-down resistor of the P56/INTP05/DRST pin.
PAGE 1393
V850ES/JG3-H, V850ES/JH3-H CHAPTER 32 ON-CHIP DEBUG FUNCTION 32.1.5 Operation The on-chip debug function is made invalid under the conditions shown in the table below. When this function is not used, keep the DRST pin low until the OCDM.OCDM0 flag is cleared to 0. OCDM0 Flag 0 1 L Invalid Invalid H Invalid Valid DRST Pin Remark L: Low-level input H: High-level input Figure 32-2.
PAGE 1394
V850ES/JG3-H, V850ES/JH3-H CHAPTER 32 ON-CHIP DEBUG FUNCTION 32.2 Debugging Without Using DCU The following describes how to implement an on-chip debug function using MINICUBE2 with pins for UARTC0 (RXDC0 and TXDC0), pins for CSIF0 (SIF0, SOF0, SCKF0, and HS (P913)), or pins for CSIF3 (SIF3, SOF3, SCKF3, and HS (P913)) as debug interfaces, without using the DCU. 32.2.1 Circuit connection examples Figure 32-3.
PAGE 1395
V850ES/JG3-H, V850ES/JH3-H CHAPTER 32 ON-CHIP DEBUG FUNCTION Table 32-3. Wiring Between V850ES/JG3-H and MINICUBE2 Pin Configuration of MINICUBE2 (QB-MINI2) Signal Name I/O Pin Function With CSIF0-HS With CSIF3-HS Pin Name Pin Name Pin No. SI/RxD Input Pin to receive commands and data from P41/SOF0 Pin With UARTC0 Pin Name No. Pin No.
PAGE 1396
V850ES/JG3-H, V850ES/JH3-H CHAPTER 32 ON-CHIP DEBUG FUNCTION Table 32-4. Wiring Between V850ES/JH3-H and MINICUBE2 Pin Configuration of MINICUBE2 (QB-MINI2) Signal Name I/O Pin Function With CSIF0-HS With CSIF3-HS Pin Name Pin Name Pin No. SI/RXD Input Pin to receive commands and data from Pin With UARTC0 Pin Name No. Pin No.
PAGE 1397
V850ES/JG3-H, V850ES/JH3-H CHAPTER 32 ON-CHIP DEBUG FUNCTION 32.2.2 Maskable functions Only reset signals can be masked. The functions that can be masked in the debugger (ID850QB) and the corresponding functions of the V850ES/JG3-H and V850ES/JH3-H are listed below. Table 32-5. Maskable Functions Functions Maskable in ID850QB Corresponding Functions of V850ES/JG3-H and V850ES/JH3-H NMI0 − NMI1 − NMI2 − STOP − HOLD − RESET WAIT R01UH0042EJ0500 Rev.5.
PAGE 1398
V850ES/JG3-H, V850ES/JH3-H CHAPTER 32 ON-CHIP DEBUG FUNCTION 32.2.3 Securement of user resources The user must prepare the following to perform communication between MINICUBE2 and the target device and implement each debug function. These items need to be set in the user program or using the compiler options. (1) Securement of memory space The shaded portions in Figure 32-4 are the areas reserved for placing the debug monitor program, so user programs and data cannot be allocated in these spaces.
PAGE 1399
V850ES/JG3-H, V850ES/JH3-H CHAPTER 32 ON-CHIP DEBUG FUNCTION Figure 32-4. Memory Spaces Where Debug Monitor Programs Are Allocated Internal ROM Internal RAM 3FFEFFFH 3FFEFF0H Note 1 (16 bytes) (2 KB) Internal RAM area Note 3 0000400HNote 2 0000070H CSI0/UART receive interrupt vector (4 bytes) Access-prohibited area Internal ROM area Security ID area (10 bytes) 0000060H Interrupt vector for debugging (4 bytes) 0000000H Reset vector (4 bytes) : Debugging area Notes 1.
PAGE 1400
V850ES/JG3-H, V850ES/JH3-H CHAPTER 32 ON-CHIP DEBUG FUNCTION (3) Reset vector A reset vector includes the jump instruction for the debug monitor program. [How to secure areas] It is not necessary to secure this area intentionally. When downloading a program, however, the debugger rewrites the reset vector in accordance with the following cases. If the rewritten pattern does not match the following cases, the debugger generates an error (F0C34 when using the ID850QB).
PAGE 1401
V850ES/JG3-H, V850ES/JH3-H CHAPTER 32 ON-CHIP DEBUG FUNCTION (4) Securement of area for debug monitor program The shaded portions in Figure 32-4 are the areas where the debug monitor program is allocated. The monitor program performs initialization processing for debug communication interface and RUN or break processing for the CPU. The internal ROM area must be filled with 0xFF. This area must not be rewritten by the user program.
PAGE 1402
V850ES/JG3-H, V850ES/JH3-H CHAPTER 32 ON-CHIP DEBUG FUNCTION (5) Securement of communication serial interface UARTC0, CSIF0, or CSIF3 is used for communication between MINICUBE2 and the target system. The settings related to the serial interface modes are performed by the debug monitor program, but if the setting is changed by the user program, a communication error may occur. To prevent such a problem from occurring, communication serial interface must be secured in the user program.
PAGE 1403
V850ES/JG3-H, V850ES/JH3-H CHAPTER 32 ON-CHIP DEBUG FUNCTION • Port registers when UARTC0 is used When UARTC0 is used, port registers are set to make the TXDC0 and RXDC0 pins valid by the debug monitor program. Do not change the following register settings with the user program during debugging. (The same value can be overwritten.
PAGE 1404
V850ES/JG3-H, V850ES/JH3-H CHAPTER 32 ON-CHIP DEBUG FUNCTION • Port registers when CSIF3 is used When CSIF3 is used for communication, port registers are set to make the SIF3, SOF3, SCKF3, and HS (P913) pins valid by the debug monitor program. Do not change the following register settings with the user program during debugging. (The same value can be overwritten.
PAGE 1405
V850ES/JG3-H, V850ES/JH3-H CHAPTER 32 ON-CHIP DEBUG FUNCTION 32.2.4 Cautions (1) Handling of device that was used for debugging Do not mount a device that was used for debugging on a mass-produced product, because the flash memory was rewritten during debugging and the number of rewrites of the flash memory cannot be guaranteed. Moreover, do not embed the debug monitor program into mass-produced products.
PAGE 1406
V850ES/JG3-H, V850ES/JH3-H CHAPTER 32 ON-CHIP DEBUG FUNCTION 32.3 ROM Security Function 32.3.1 Security ID The flash memory versions of the V850ES/JG3-H and V850ES/JH3-H perform authentication using a 10-byte ID code to prevent the contents of the flash memory from being read by an unauthorized person during on-chip debugging by the on-chip debug emulator. Set the ID code in the 10-byte on-chip flash memory area from 0000070H to 0000079H to allow the debugger perform ID authentication.
PAGE 1407
V850ES/JG3-H, V850ES/JH3-H CHAPTER 32 ON-CHIP DEBUG FUNCTION 32.3.2 Setting The following shows how to set the ID code as shown in Table 32-6. When the ID code is set as shown in Table 32-6, the ID code input in the configuration dialog box of the ID850QB is “123456789ABCDEF123D4” (the ID code is case-insensitive). Table 32-6.
PAGE 1408
V850ES/JG3-H, V850ES/JH3-H CHAPTER 32 ON-CHIP DEBUG FUNCTION [Program example (when using CA850 Ver. 3.10 or later)] #-------------------------------------# SECURITYID #-------------------------------------.section "SECURITY_ID" --Interrupt handler address 0x70 .word 0x78563412 --0-3 byte code .word 0xF1DEBC9A --4-7 byte code .hword 0xD423 --8-9 byte code Remark Add the above program example to the startup files. R01UH0042EJ0500 Rev.5.
PAGE 1409
V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS CHAPTER 33 ELECTRICAL SPECIFICATIONS 33.1 Absolute Maximum Ratings (TA = 25°C) (1/2) Parameter Supply voltage Input voltage Symbol Conditions Ratings Unit VDD VDD = EVDD = UVDD = AVREF0 = AVREF1 −0.5 to +4.6 V EVDD VDD = EVDD = UVDD = AVREF0 = AVREF1 −0.5 to +4.6 V UVDD VDD = EVDD = UVDD = AVREF0 = AVREF1 −0.5 to +4.6 V AVREF0 VDD = EVDD = UVDD = AVREF0 = AVREF1 −0.5 to +4.
PAGE 1410
V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS (TA = 25°C) (2/2) Parameter Output current, low Symbol IOL Conditions P00 to P05, P20 to P25, P30 to P37 Ratings Unit Per pin 4 mA Total of all pins 50 mA Per pin 4 mA Total of all pins 8 mA Per pin 4 mA Total of all pins 8 mA Per pin 4 mA Total of all pins 20 mA Per pin −4 mA Total of all pins −50 mA Per pin −4 mA Total of all pins −8 mA Per pin −4 mA Total of all pins −8 mA Per pin −4 mA Tot
PAGE 1411
V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS 33.2 Capacitance (TA = 25°C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V) Parameter I/O capacitance Symbol CIO Conditions MIN. TYP. fX = 1 MHz MAX. 10 Unit pF Measured pins returned to 0 V 33.
PAGE 1412
V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS 33.4 Oscillator Characteristics 33.4.1 Main clock oscillator characteristics (TA = −40 to +85°C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF) Resonator Ceramic Circuit Example X1 X2 Parameter Conditions MIN. TYP. 3 Oscillation frequency MAX.
PAGE 1413
V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS (1) KYOCERA KINSEKI CORPORATION: Crystal resonator Type Circuit Example Part Number Oscillation Recommended Circuit Oscillation Voltage Oscillation Frequency Constant Range Stabilization fX (MHz) Time C1 (pF) C2 (pF) Rd (Ω) MIN. (V) MAX. (V) Surface mounting X1 4.000 10 10 1000 2.85 MAX. (ms) 3.6 14.86 Rd C1 Caution CX49GFWB04000D0PPTZ1 X2 C2 CX49GFWB05000D0PPTZ1 5.000 10 10 1000 2.85 3.6 13.
PAGE 1414
V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS The oscillation voltage and oscillation frequency indicate only oscillator characteristics. Use the V850ES/Jx3-H so that the internal operating conditions are within the specifications of the DC and AC characteristics. Remark Figures in parentheses in columns C1 and C2 indicate the capacitance incorporated in the resonator. 33.4.
PAGE 1415
V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS (1) Seiko Instruments Inc.: Crystal resonator Oscillation frequency: fXT = 32.768 kHz Type Circuit Example Part Number Recommended Circuit Oscillation Voltage Oscillation Constant Range Stabilization Time C1 (pF) C2 (pF) Rd (Ω) MIN. (V) MAX. (V) Surface mounting SSP-T7 XT1 7 7 0 2.85 3.6 MAX. (ms) 1.
PAGE 1416
V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS 33.4.3 PLL characteristics (TA = −40 to +85°C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Input frequency fX Output frequency fXX Lock time Conditions MIN. TYP. MAX. Unit 3 6 MHz Clock-through mode 3 6 MHz PLL mode (×8) 24 48 MHz 800 μs tPLL 33.4.
PAGE 1417
V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS 33.5 DC Characteristics 33.5.1 I/O level (TA = −40 to +85°C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF) Parameter Input voltage, high Symbol VIH1 Conditions RESET, FLMD0, P60 to P65 MIN. TYP. MAX. Unit 0.8EVDD EVDD V P90 to P915 VIH2 P00 to P05, P20 to P25, P30 to P35, P42, P50 to P56 0.8EVDD 5.5 V VIH3 P36, P37, P40, P41, PCM2, PCM3 0.7EVDD 5.5 V PDL0 to PDL15, PDH0 to PDH7, PCM0, 0.
PAGE 1418
V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF) Parameter Output voltage, high Symbol VOH1 Conditions Note 1 Per pin MIN. TYP. MAX. Unit EVDD − 1.0 EVDD V EVDD − 0.5 EVDD V AVREF0 − 1.0 AVREF0 V AVREF0 − 0.5 AVREF0 V AVREF1 − 1.0 AVREF1 V AVREF1 − 0.5 AVREF1 V IOH = −1.0 mA Per pin IOH = −100 μA VOH2 P70 to P711 Per pin IOH = −0.
PAGE 1419
V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS 33.5.2 Supply current (TA = −40 to +85°C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF) Parameter Supply current Notes 1, 2 Symbol IDD1 Conditions Normal operation MIN. TYP. fXX = 48 MHz (fX = 6 MHz) Peripheral function operating MAX. 120 fXX = 48 MHz (fX = 6 MHz) 54 Unit mA mA USBF operating IDD2 HALT mode fXX = 48 MHz (fX = 6 MHz) 42 60 mA 4 7 mA 0.
PAGE 1420
V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS 33.6 Data Retention Characteristics (1) In STOP mode (TA = −40 to +85°C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Data retention voltage VDDDR Conditions MIN. STOP mode (all functions TYP. 1.9 MAX. Unit 3.
PAGE 1421
V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS 33.
PAGE 1422
V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS 33.7.1 CLKOUT output timing (TA = −40 to +85°C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. MAX. Unit 31.25 μs Output cycle tCYK <1> 20.83 ns High-level width tWKH <2> tCYK/2 − 6 ns Low-level width tWKL <3> tCYK/2 − 6 ns Rise time tKR <4> 6 ns Fall time tKF <5> 6 ns Clock Timing <1> <2> <3> CLKOUT (output) <4> R01UH0042EJ0500 Rev.5.
PAGE 1423
V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS 33.7.2 Bus timing (1) In multiplexed bus mode/separate bus mode (a) Read/write cycle (CLKOUT asynchronous) (TA = −40 to +85°C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. MAX. Unit Address setup time (to ASTB↓) tDAST <6> (0.5 + tASw)T − 9 ns Address hold time (from ASTB↓) tHSTA <7> (0.
PAGE 1424
V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS Read Cycle (CLKOUT Asynchronous): In Multiplexed Bus Mode/Separate Bus Mode T1 T2 TW T3 Ti T1 CLKOUT (output) <31> CS0, CS2, CS3 (output) A0 to A23 (output)Note <9> AD0 to AD15 (I/O) Hi-Z Address <6> Data <7> <12> ASTB (output) <14> <17> <29> <8> <11> <10> <13> <15> RD (output) <16> <25> <27> <26> <28> WAIT (input) <21> <23> <22> <24> Note V850ES/JH3-H only Remark WR0 and WR1 are high level. R01UH0042EJ0500 Rev.5.
PAGE 1425
V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS Write Cycle (CLKOUT Asynchronous): In Multiplexed Bus Mode/Separate Bus Mode T1 T2 TW T3 T1 CLKOUT (output) <32> CS0, CS2 CS3 (output) A0 to A23 (output)Note <30> AD0 to AD15 (I/O) Address <6> ASTB (output) Data <7> <17> <18> <11> <14> <19> <20> WR0, WR1 (output) <16> <25> <27> <26> <28> WAIT (input) <21> <23> <22> <24> Note V850ES/JH3-H only Remark RD is high level. R01UH0042EJ0500 Rev.5.
PAGE 1426
V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS (b) Read/write cycle (CLKOUT synchronous): In multiplexed bus mode/separate bus mode (TA = −40 to +85°C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. MAX.
PAGE 1427
V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS Write Cycle (CLKOUT Synchronous): In Multiplexed Bus Mode/Separate Bus Mode T1 T2 TW T3 T1 CLKOUT (output) <33> CS0, CS2, CS3 (output) <33> <42> A16 to A23 (output)Note <43> <39> AD0 to AD15 (I/O) Address Data <35> <35> ASTB (output) WR0, WR1 (output) <36> <36> WAIT (input) <40> Note V850ES/JH3-H only Remark RD is high level. R01UH0042EJ0500 Rev.5.
PAGE 1428
V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS (2) During bus hold (V850ES/JH3-H only) (a) CLKOUT asynchronous (TA = −40 to +85°C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. MAX. Unit HLDRQ high-level width tWHQH <44> T + 16 ns HLDAK low-level width tWHAL <45> T − 10 ns Delay time from HLDAK↑ to bus output tDHAC <46> −7 ns Delay time from HLDRQ↓ to HLDAK↓ tDHQHA1 <47> 2.
PAGE 1429
V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS (b) CLKOUT synchronous (TA = −40 to +85°C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. MAX.
PAGE 1430
V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS 33.8 Basic Operation (1) Power on/power off/reset timing (TA = −40 to +85°C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. MAX.
PAGE 1431
V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS (2) Reset, interrupt timing (TA = −40 to +85°C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol RESET input low-level width tWRSL NMI high-level width tWNIH NMI low-level width INTPn high-level width INTPn low-level width Remark Conditions MIN. MAX.
PAGE 1432
V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS (3) Timer timing (TA = −40 to +85°C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF) Parameter TI high-level width Symbol tTIH Conditions MIN. TAB00 to TAB03,TAB10 to TAB13, MAX.
PAGE 1433
V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS (4) UARTC timing (TA = −40 to +85°C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. MAX. Unit Transmit rate 3.0 Mbps ASCK0 cycle time 10 MHz R01UH0042EJ0500 Rev.5.
PAGE 1434
V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS (5) CSIF timing (a) Master mode [When using CSI0 to CSIF2, or CSIF4] (TA = −40 to +85°C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. MAX.
PAGE 1435
V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS (b) Slave mode [When using CSI0 to CSIF2, or CSIF4] (TA = −40 to +85°C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. MAX.
PAGE 1436
V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS (a) CFnCTL1.CFnCKP, CFnDAP bits = 00 or 11 <63> <64> <64> SCKFn (I/O) <68> <65> SIFn (input) <66> Input data <67> Output data SOFn (output) (b) CFnCTL1.CFnCKP, CFnDAP bits = 10 or 01 <63> <64> <64> SCKFn (I/O) <68> <65> SIFn (input) <66> Input data <67> SOFn (output) Remark Output data n = 0 to 4 R01UH0042EJ0500 Rev.5.
PAGE 1437
V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS 2 (6) I C bus mode (TA = −40 to +85°C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V) Parameter Symbol Normal Mode High-Speed Mode Unit MIN. MAX. MIN. MAX. 0 100 0 400 SCL0n clock frequency fCLK kHz Bus free time tBUF <69> 4.7 − 1.3 − μs tHD:STA <70> 4.0 − 0.6 − μs SCL0n clock low-level width tLOW <71> 4.7 − 1.3 − μs SCL0n clock high-level width tHIGH <72> 4.0 − 0.
PAGE 1438
V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS <71> <72> SCL0n (I/O) <77> <76> <74> <75> <73> <70> <79> <78> <70> SDA0n (I/O) <69> <76> Stop Start condition condition Remark <77> Restart condition Stop condition n = 0 to 2 R01UH0042EJ0500 Rev.5.
PAGE 1439
V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS (7) CAN timing (CAN controller versions only) (TA = −40 to +85°C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. Transmit rate MAX.
PAGE 1440
V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS (8) High-impedance control timing (TA = −40 to +85°C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Time from oscillator stop to timer output high impedance tCLM Conditions MIN. Clock monitor MAX.
PAGE 1441
V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS (10) D/A converter (TA = −40 to +85°C, VDD = EVDD = UVDD = AVREF0 = AVREF1, 3.0 V ≤ AVREF1 ≤ 3.6 V, VSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. TYP. Resolution MAX. 8 Note 1 bit Overall error R = 2 MΩ ±1.2 Settling time C = 20 pF 3 Output resistor RO Reference voltage AVREF1 AVREF1 current Note 2 AIREF1 Output data 55H D/A conversion operating 1 D/A conversion stopped %FSR μs 6.42 3.
PAGE 1442
V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS (12) RAM retention detection (TA = −40 to +85°C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions Detection voltage VRAMH Supply voltage rise time tRAMHTH VDD = 0 to 2.85 V tRAMHD After VDD reaches 2.1 V Response time Note Minimum pulse width tRAMHW MIN. TYP. MAX. 1.9 2.0 2.1 0.002 Unit V ms 0.2 3.0 0.
PAGE 1443
V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS 33.9 Flash Memory Programming Characteristics (TA = −40 to +85°C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF) (1) Basic characteristics Parameter Symbol Conditions MIN. TYP. MAX. Unit Operating frequency fCPU 24 48 MHz Supply voltage VDD 2.85 3.
PAGE 1444
V850ES/JG3-H, V850ES/JH3-H CHAPTER 33 ELECTRICAL SPECIFICATIONS (2) Serial write operation characteristics Parameter Symbol FLMD0, FLMD1 setup time tMDSET FLMD0 count start time from RESET↑ tRFCF FLMD0 counter high-level width/ low-level width tCH/tCL FLMD0 counter rise time/fall time tR/tF Conditions MIN. 2 fX = 3 to 6 MHz TYP. MAX.
PAGE 1445
V850ES/JG3-H, V850ES/JH3-H CHAPTER 34 PACKAGE DRAWINGS CHAPTER 34 PACKAGE DRAWINGS 100-PIN PLASTIC LQFP (FINE PITCH) (14x14) HD detail of lead end D L1 75 76 51 50 A3 c θ E L HE Lp (UNIT:mm) 26 25 100 1 ZE e b ZD x M S A A2 S y S A1 ITEM D DIMENSIONS 14.00±0.20 E 14.00±0.20 HD 16.00±0.20 HE 16.00±0.20 A 1.60 MAX. A1 0.10±0.05 A2 1.40± 0.05 A3 0.25 b 0.20 + 0.07 0.03 c 0.125 + 0.075 0.025 L 0.50 Lp 0.60±0.15 L1 e 1.00±0.20 3° + 5° 3° 0.50 x 0.08 y 0.
PAGE 1446
V850ES/JG3-H, V850ES/JH3-H CHAPTER 34 PACKAGE DRAWINGS 128-PIN PLASTIC LQFP (FINE PITCH) (14x20) HD D detail of lead end 102 103 65 64 A3 c E HE θ L Lp 128 1 L1 39 38 ZE ZD b x M S (UNIT:mm) e A A2 S ITEM D DIMENSIONS 20.00±0.20 E 14.00±0.20 HD 22.00±0.20 HE 16.00±0.20 A 1.60 MAX. A1 0.10±0.05 A2 1.40±0.05 A3 y S NOTE Each lead centerline is located within 0.08 mm of its true position at maximum material condition. A1 0.20 +0.07 −0.03 c 0.125 +0.075 −0.025 L 0.
PAGE 1447
V850ES/JG3-H, V850ES/JH3-H CHAPTER 35 RECOMMENDED SOLDERING CONDITIONS CHAPTER 35 RECOMMENDED SOLDERING CONDITIONS These products should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, please contact a Renesas Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www2.renesas.com/pkg/en/mount/index.
PAGE 1448
V850ES/JG3-H, V850ES/JH3-H CHAPTER 35 RECOMMENDED SOLDERING CONDITIONS Table 35-1.
PAGE 1449
V850ES/JG3-H, V850ES/JH3-H APPENDIX A DEVELOPMENT TOOLS APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the V850ES/JG3-H or V850ES/JH3-H. Figure A-1 shows the development tool configuration. • Support for PC98-NX series Unless otherwise specified, products supported by IBM PC/ATTM compatibles are compatible with PC98-NX series computers. When using PC98-NX series computers, refer to the explanation for IBM PC/AT compatibles.
PAGE 1450
V850ES/JG3-H, V850ES/JH3-H APPENDIX A DEVELOPMENT TOOLS Figure A-1.
PAGE 1451
V850ES/JG3-H, V850ES/JH3-H APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP850 Development tools (software) commonly used with V850 microcontrollers are included this Software package for V850 microcontrollers package. Remark Part number: μS××××SP850 ×××× in the part number differs depending on the host machine and OS used. μS××××SP850 ×××× AB17 BB17 Host Machine PC-9800 series, IBM PC/AT compatibles OS Windows (Japanese version) Supply Medium CD-ROM Windows (English version) A.
PAGE 1452
V850ES/JG3-H, V850ES/JH3-H APPENDIX A DEVELOPMENT TOOLS A.4 Debugging Tools (Hardware) A.4.1 When using IECUBE QB-V850ESJX3H The system configuration when connecting the QB-V850ESJX3H to the host machine (PC-9821 series, PC/AT compatible) is shown below. Even if optional products are not prepared, connection is possible. Figure A-2.
PAGE 1453
V850ES/JG3-H, V850ES/JH3-H APPENDIX A DEVELOPMENT TOOLS Figure A-2. System Configuration (When Using QB-V850ESJX3H) (2/2) <1> Host machine (PC-9821 series, IBM-PC/AT compatibles) <2> Debugger, USB driver, manuals, etc.
PAGE 1454
V850ES/JG3-H, V850ES/JH3-H Note APPENDIX A DEVELOPMENT TOOLS <5> QB-V850ESJX3H The in-circuit emulator serves to debug hardware and software when developing In-circuit emulator application systems using the V850ES/JG3-H or V850ES/JH3-H. It supports the integrated debugger ID850QB. This emulator should be used in combination with a power supply unit and emulation probe. Use the USB interface cable to connect this emulator to the host machine.
PAGE 1455
V850ES/JG3-H, V850ES/JH3-H A.4.2 APPENDIX A DEVELOPMENT TOOLS When using MINICUBE QB-V850MINI (1) On-chip emulation using MINICUBE The system configuration when connecting MINICUBE to the host machine (PC-9821 series, PC/AT compatible) is shown below. Figure A-3.
PAGE 1456
V850ES/JG3-H, V850ES/JH3-H A.4.3 APPENDIX A DEVELOPMENT TOOLS When using MINICUBE2 QB-MINI2 The system configuration when connecting MINICUBE2 to the host machine (PC-9821 series, PC/AT compatible) is shown below. Figure A-4. System Configuration of On-Chip Emulation System <4> <3> <1> <5> V850ES/JG3-H, V850ES/JH3-H M IN IC U BE 2 <6> <2> Software Target system <1> Host machine PC with USB ports <2> Software The integrated debugger ID850QB, device file, etc.
PAGE 1457
V850ES/JG3-H, V850ES/JH3-H APPENDIX A DEVELOPMENT TOOLS A.6 Embedded Software RX850, RX850 Pro The RX850 and RX850 Pro are real-time OSs conforming to μITRON 3.0 specifications. Real-time OS A tool (configurator) for generating multiple information tables is supplied. RX850 Pro has more functions than the RX850. Part number: μS××××RX703000-ΔΔΔΔ (RX850) μS××××RX703100-ΔΔΔΔ (RX850 Pro) RX-FS850 This is a FAT file system function.
PAGE 1458
V850ES/JG3-H, V850ES/JH3-H APPENDIX B MAJOR DIFFERENCES BETWEEN V850ES/Jx3-H AND V850ES/Jx3 APPENDIX B MAJOR DIFFERENCES BETWEEN V850ES/Jx3-H AND V850ES/Jx3 Table B-1. Major Differences Between V850ES/Jx3-H and V850ES/Jx3 Major Difference V850ES/Jx3-H V850ES/Jx3 Minimum instruction execution time 20.8 ns (48 MHz operation) 31.
PAGE 1459
V850ES/JG3-H, V850ES/JH3-H APPENDIX C REGISTER INDEX APPENDIX C REGISTER INDEX (1/37) Symbol Name Unit Page ADA0CR0 A/D conversion result register 0 ADC 690 ADA0CR0H A/D conversion result register 0H ADC 690 ADA0CR1 A/D conversion result register 1 ADC 690 ADA0CR1H A/D conversion result register 1H ADC 690 ADA0CR2 A/D conversion result register 2 ADC 690 ADA0CR2H A/D conversion result register 2H ADC 690 ADA0CR3 A/D conversion result register 3 ADC 690 ADA0CR3H A/D conver
PAGE 1460
V850ES/JG3-H, V850ES/JH3-H APPENDIX C REGISTER INDEX (2/37) Symbol Name Unit Page C0BRP CAN0 module bit rate prescaler register CAN 960 C0BTR CAN0 module bit rate register CAN 962 C0CTRL CAN0 module control register CAN 950 C0ERC CAN0 module error counter register CAN 956 C0GMABT CAN0 global automatic block transmission control register CAN 945 C0GMABTD CAN0 global automatic block transmission delay setting register CAN 947 C0GMCS CAN0 global clock selection register CAN 944
PAGE 1461
V850ES/JG3-H, V850ES/JH3-H APPENDIX C REGISTER INDEX (3/37) Symbol Name Unit Page C0MCONF18 CAN0 message configuration register 18 CAN 972 C0MCONF19 CAN0 message configuration register 19 CAN 972 C0MCONF20 CAN0 message configuration register 20 CAN 972 C0MCONF21 CAN0 message configuration register 21 CAN 972 C0MCONF22 CAN0 message configuration register 22 CAN 972 C0MCONF23 CAN0 message configuration register 23 CAN 972 C0MCONF24 CAN0 message configuration register 24 CAN 97
PAGE 1462
V850ES/JG3-H, V850ES/JH3-H APPENDIX C REGISTER INDEX (4/37) Symbol Name Unit Page C0MCTRL26 CAN0 message control register 26 CAN 974 C0MCTRL27 CAN0 message control register 27 CAN 974 C0MCTRL28 CAN0 message control register 28 CAN 974 C0MCTRL29 CAN0 message control register 29 CAN 974 C0MCTRL30 CAN0 message control register 30 CAN 974 C0MCTRL31 CAN0 message control register 31 CAN 974 C0MDATA000 CAN0 message data byte 0 register 00 CAN 969 C0MDATA001 CAN0 message data byte
PAGE 1463
V850ES/JG3-H, V850ES/JH3-H APPENDIX C REGISTER INDEX (5/37) Symbol Name Unit Page C0MDATA0121 CAN0 message data byte 01 register 21 CAN 969 C0MDATA0122 CAN0 message data byte 01 register 22 CAN 969 C0MDATA0123 CAN0 message data byte 01 register 23 CAN 969 C0MDATA0124 CAN0 message data byte 01 register 24 CAN 969 C0MDATA0125 CAN0 message data byte 01 register 25 CAN 969 C0MDATA0126 CAN0 message data byte 01 register 26 CAN 969 C0MDATA0127 CAN0 message data byte 01 register 27
PAGE 1464
V850ES/JG3-H, V850ES/JH3-H APPENDIX C REGISTER INDEX (6/37) Symbol Name Unit Page C0MDATA110 CAN0 message data byte 1 register 10 CAN 969 C0MDATA111 CAN0 message data byte 1 register 11 CAN 969 C0MDATA112 CAN0 message data byte 1 register 12 CAN 969 C0MDATA113 CAN0 message data byte 1 register 13 CAN 969 C0MDATA114 CAN0 message data byte 1 register 14 CAN 969 C0MDATA115 CAN0 message data byte 1 register 15 CAN 969 C0MDATA116 CAN0 message data byte 1 register 16 CAN 969 C0MD
PAGE 1465
V850ES/JG3-H, V850ES/JH3-H APPENDIX C REGISTER INDEX (7/37) Symbol Name Unit Page C0MDATA218 CAN0 message data byte 2 register 18 CAN 969 C0MDATA219 CAN0 message data byte 2 register 19 CAN 969 C0MDATA220 CAN0 message data byte 2 register 20 CAN 969 C0MDATA221 CAN0 message data byte 2 register 21 CAN 969 C0MDATA222 CAN0 message data byte 2 register 22 CAN 969 C0MDATA223 CAN0 message data byte 2 register 23 CAN 969 C0MDATA224 CAN0 message data byte 2 register 24 CAN 969 C0MD
PAGE 1466
V850ES/JG3-H, V850ES/JH3-H APPENDIX C REGISTER INDEX (8/37) Symbol Name Unit Page C0MDATA2326 CAN0 message data byte 23 register 26 CAN 969 C0MDATA2327 CAN0 message data byte 23 register 27 CAN 969 C0MDATA2328 CAN0 message data byte 23 register 28 CAN 969 C0MDATA2329 CAN0 message data byte 23 register 29 CAN 969 C0MDATA2330 CAN0 message data byte 23 register 30 CAN 969 C0MDATA2331 CAN0 message data byte 23 register 31 CAN 969 C0MDATA300 CAN0 message data byte 3 register 00 CA
PAGE 1467
V850ES/JG3-H, V850ES/JH3-H APPENDIX C REGISTER INDEX (9/37) Symbol Name Unit Page C0MDATA402 CAN0 message data byte 4 register 02 CAN 969 C0MDATA403 CAN0 message data byte 4 register 03 CAN 969 C0MDATA404 CAN0 message data byte 4 register 04 CAN 969 C0MDATA405 CAN0 message data byte 4 register 05 CAN 969 C0MDATA406 CAN0 message data byte 4 register 06 CAN 969 C0MDATA407 CAN0 message data byte 4 register 07 CAN 969 C0MDATA408 CAN0 message data byte 4 register 08 CAN 969 C0MD
PAGE 1468
V850ES/JG3-H, V850ES/JH3-H APPENDIX C REGISTER INDEX (10/37) Symbol Name Unit Page C0MDATA4510 CAN0 message data byte 45 register 10 CAN 973 C0MDATA4511 CAN0 message data byte 45 register 11 CAN 973 C0MDATA4512 CAN0 message data byte 45 register 12 CAN 973 C0MDATA4513 CAN0 message data byte 45 register 13 CAN 973 C0MDATA4514 CAN0 message data byte 45 register 14 CAN 973 C0MDATA4515 CAN0 message data byte 45 register 15 CAN 973 C0MDATA4516 CAN0 message data byte 45 register 16
PAGE 1469
V850ES/JG3-H, V850ES/JH3-H APPENDIX C REGISTER INDEX (11/37) Symbol Name Unit Page C0MDATA518 CAN0 message data byte 5 register 18 CAN 969 C0MDATA519 CAN0 message data byte 5 register 19 CAN 969 C0MDATA520 CAN0 message data byte 5 register 20 CAN 969 C0MDATA521 CAN0 message data byte 5 register 21 CAN 969 C0MDATA522 CAN0 message data byte 5 register 22 CAN 969 C0MDATA523 CAN0 message data byte 5 register 23 CAN 969 C0MDATA524 CAN0 message data byte 5 register 24 CAN 969 C0M
PAGE 1470
V850ES/JG3-H, V850ES/JH3-H APPENDIX C REGISTER INDEX (12/37) Symbol Name Unit Page C0MDATA626 CAN0 message data byte 6 register 26 CAN 969 C0MDATA627 CAN0 message data byte 6 register 27 CAN 969 C0MDATA628 CAN0 message data byte 6 register 28 CAN 969 C0MDATA629 CAN0 message data byte 6 register 29 CAN 969 C0MDATA630 CAN0 message data byte 6 register 30 CAN 969 C0MDATA631 CAN0 message data byte 6 register 31 CAN 969 C0MDATA6700 CAN0 message data byte 67 register 00 CAN 969 C
PAGE 1471
V850ES/JG3-H, V850ES/JH3-H APPENDIX C REGISTER INDEX (13/37) Symbol Name Unit Page C0MDATA702 CAN0 message data byte 7 register 02 CAN 969 C0MDATA703 CAN0 message data byte 7 register 03 CAN 969 C0MDATA704 CAN0 message data byte 7 register 04 CAN 969 C0MDATA705 CAN0 message data byte 7 register 05 CAN 969 C0MDATA706 CAN0 message data byte 7 register 06 CAN 969 C0MDATA707 CAN0 message data byte 7 register 07 CAN 969 C0MDATA708 CAN0 message data byte 7 register 08 CAN 969 C0M
PAGE 1472
V850ES/JG3-H, V850ES/JH3-H APPENDIX C REGISTER INDEX (14/37) Symbol Name Unit Page C0MDLC10 CAN0 message data length register 10 CAN 971 C0MDLC11 CAN0 message data length register 11 CAN 971 C0MDLC12 CAN0 message data length register 12 CAN 971 C0MDLC13 CAN0 message data length register 13 CAN 971 C0MDLC14 CAN0 message data length register 14 CAN 971 C0MDLC15 CAN0 message data length register 15 CAN 971 C0MDLC16 CAN0 message data length register 16 CAN 971 C0MDLC17 CAN0 me
PAGE 1473
V850ES/JG3-H, V850ES/JH3-H APPENDIX C REGISTER INDEX (15/37) Symbol Name Unit Page C0MIDH18 CAN0 message identifier register 18H CAN 973 C0MIDH19 CAN0 message identifier register 19H CAN 973 C0MIDH20 CAN0 message identifier register 20H CAN 973 C0MIDH21 CAN0 message identifier register 21H CAN 973 C0MIDH22 CAN0 message identifier register 22H CAN 973 C0MIDH23 CAN0 message identifier register 23H CAN 973 C0MIDH24 CAN0 message identifier register 24H CAN 973 C0MIDH25 CAN0 me
PAGE 1474
V850ES/JG3-H, V850ES/JH3-H APPENDIX C REGISTER INDEX (16/37) Symbol Name Unit Page C0MIDL26 CAN0 message identifier register 26L CAN 973 C0MIDL27 CAN0 message identifier register 27L CAN 973 C0MIDL28 CAN0 message identifier register 28L CAN 973 C0MIDL29 CAN0 message identifier register 29L CAN 973 C0MIDL30 CAN0 message identifier register 30L CAN 973 C0MIDL31 CAN0 message identifier register 31L CAN 973 C0RGPT CAN0 module receive history list register CAN 964 C0TGPT CAN0 m
PAGE 1475
V850ES/JG3-H, V850ES/JH3-H APPENDIX C REGISTER INDEX (17/37) Symbol Name Unit Page CF3CTL2 CSIF3 control register 2 CSIF 773 CF3RIC Interrupt control register INTC 1264 CF3RX CSIF3 receive data register CSIF 767 CF3RXL CSIF3 receive data register L CSIF 767 CF3STR CSIF3 status register CSIF 775 CF3TIC Interrupt control register INTC 1265 CF3TX CSIF3 transmit data register CSIF 768 CF3TXL CSIF3 transmit data register L CSIF 768 CF4CTL0 CSIF4 control register 0 CSIF 76
PAGE 1476
V850ES/JG3-H, V850ES/JH3-H APPENDIX C REGISTER INDEX (18/37) Symbol Name Unit Page DCHC3 DMA channel control register 3 DMAC 1238 DDA0H DMA destination address register 0H DMAC 1235 DDA0L DMA destination address register 0L DMAC 1235 DDA1H DMA destination address register 1H DMAC 1235 DDA1L DMA destination address register 1L DMAC 1235 DDA2H DMA destination address register 2H DMAC 1235 DDA2L DMA destination address register 2L DMAC 1235 DDA3H DMA destination address regis
PAGE 1477
V850ES/JG3-H, V850ES/JH3-H APPENDIX C REGISTER INDEX (19/37) Symbol IICCL0 IICCL1 IICCL2 Name IIC clock select register 0 IIC clock select register 1 IIC clock select register 2 Unit Page 2 832 2 832 2 832 2 832 2 832 2 IC IC IC IICF0 IIC flag register 0 IC IICF1 IIC flag register 1 IC IICF2 IIC flag register 2 IC 832 IICIC0 Interrupt control register INTC 1260 IICIC1 Interrupt control register INTC 1259 IICIC2 Interrupt control register INTC 1260 IICS0 IICS1 IIC sta
PAGE 1478
V850ES/JG3-H, V850ES/JH3-H APPENDIX C REGISTER INDEX (20/37) Symbol Name Unit Page INTR2 External rising edge specification register 2 INTC 1396 INTR3 External rising edge specification register 3 INTC 1397 INTR4 External rising edge specification register 4 INTC 1398 INTR5 External rising edge specification register 5 INTC 1399 INTR9 External rising edge specification register 9 INTC 1300 INTR9H External rising edge specification register 9H INTC 1300 INTR9L External rising e
PAGE 1479
V850ES/JG3-H, V850ES/JH3-H APPENDIX C REGISTER INDEX (21/37) Symbol Name Unit Page PF9 Port 9 function register Port 148 PF9L Port 9 function register L Port 148 PFC0 Port 0 function control register Port 111 PFC2 Port 2 function control register Port 115 PFC3 Port 3 function control register Port 120 PFC4 Port 4 function control register Port 124 PFC5 Port 5 function control register Port 130 PFC6 Port 6 function control register Port 135 PFC9 Port 9 function control
PAGE 1480
V850ES/JG3-H, V850ES/JH3-H APPENDIX C REGISTER INDEX (22/37) Symbol Name Unit Page PM2 Port 2 mode register Port 114 PM3 Port 3 mode register Port 118 PM4 Port 4 mode register Port 123 PM5 Port 5 mode register Port 128 PM6 Port 6 mode register Port 134 PM7H Port 7 mode register H Port 138 PM7L Port 7 mode register L Port 138 PM9 Port 9 mode register Port 140 PM9H Port 9 mode register H Port 140 PM9L Port 9 mode register L Port 140 PMC0 Port 0 mode control regis
PAGE 1481
V850ES/JG3-H, V850ES/JH3-H APPENDIX C REGISTER INDEX (23/37) Symbol Name Unit Page PSMR Power save mode register CG 1309 PSW Program status word CPU 60 r0-r31 General-purpose registers CPU 56 RAMS Internal RAM data status register LVI 1344 RC1ALH Alarm hour setting register RTC 651 RC1ALM Alarm minute setting register RTC 651 RC1ALW Alarm day-of week setting register RTC 652 RC1CC0 Real-time counter control register 0 RTC 640 RC1CC1 Real-time counter control register 1
PAGE 1482
V850ES/JG3-H, V850ES/JH3-H APPENDIX C REGISTER INDEX (24/37) Symbol Name Unit Page TAA0IOC1 TAA0 I/O control register 1 Timer 222 TAA0IOC2 TAA0 I/O control register 2 Timer 223 TAA0IOC4 TAA0 I/O control register 4 Timer 224 TAA0OPT0 TAA0 option register 0 Timer 225 TAA0OPT1 TAA0 option register 1 Timer 226 TAA0OVIC Interrupt control register INTC 1280 TAA1CCIC0 Interrupt control register INTC 1280 TAA1CCIC1 Interrupt control register INTC 1280 TAA1CCR0 TAA1 capture/com
PAGE 1483
V850ES/JG3-H, V850ES/JH3-H APPENDIX C REGISTER INDEX (25/37) Symbol Name Unit Page TAA3IOC4 TAA3 I/O control register 4 Timer 224 TAA3OPT0 TAA3 option register 0 Timer 225 TAA3OVIC Interrupt control register INTC 1280 TAA4CCIC0 Interrupt control register INTC 1280 TAA4CCIC1 Interrupt control register INTC 1280 TAA4CCR0 TAA4 capture/compare register 0 Timer 227 TAA4CCR1 TAA4 capture/compare register 1 Timer 229 TAA4CNT TAA4 counter read buffer register Timer 231 TAA4CTL0
PAGE 1484
V850ES/JG3-H, V850ES/JH3-H APPENDIX C REGISTER INDEX (26/37) Symbol Name Unit Page TAB1CCIC2 Interrupt control register INTC 1280 TAB1CCIC3 Interrupt control register INTC 1280 TAB1CCR0 TAB1 capture/compare register 0 Timer 342 TAB1CCR1 TAB1 capture/compare register 1 Timer 344 TAB1CCR2 TAB1 capture/compare register 2 Timer 346 TAB1CCR3 TAB1 capture/compare register 3 Timer 348 TAB1CNT TAB1 counter read buffer register Timer 350 TAB1CTL0 TAB1 control register 0 Timer 335
PAGE 1485
V850ES/JG3-H, V850ES/JH3-H APPENDIX C REGISTER INDEX (27/37) Symbol Name Unit Page TT0IOC0 TMT0 I/O control register 0 Timer 444 TT0IOC1 TMT0 I/O control register 1 Timer 446 TT0IOC2 TMT0 I/O control register 2 Timer 447 TT0IOC3 TMT0 I/O control register 3 Timer 584 TT0OPT0 TMT0 option register 0 Timer 450 TT0OPT1 TMT0 option register 1 Timer 451 TT0OVIC Interrupt control register INTC 1280 TT0TCW TMT0 count write register Timer 457 UC0CTL0 UARTC0 control register 0 U
PAGE 1486
V850ES/JG3-H, V850ES/JH3-H APPENDIX C REGISTER INDEX (28/37) Symbol Name Unit Page UC2TXL UARTC2 transmit data register L UARTC 741 UC3CTL0 UARTC3 control register 0 UARTC 728 UC3CTL1 UARTC3 control register 1 UARTC 754 UC3CTL2 UARTC3 control register 2 UARTC 755 UC3OPT0 UARTC3 option control register 0 UARTC 730 UC3OPT1 UARTC3 option control register 1 UARTC 732 UC3RIC Interrupt control register INTC 1281 UC3RX UARTC3 receive data register UARTC 736 UC3RXL UARTC3 rece
PAGE 1487
V850ES/JG3-H, V850ES/JH3-H APPENDIX C REGISTER INDEX (29/37) Symbol Name Unit Page UF0CIE6 UF0 configuration/interface/endpoint descriptor register 6 USBF 1164 UF0CIE7 UF0 configuration/interface/endpoint descriptor register 7 USBF 1164 UF0CIE8 UF0 configuration/interface/endpoint descriptor register 8 USBF 1164 UF0CIE9 UF0 configuration/interface/endpoint descriptor register 9 USBF 1164 UF0CIE10 UF0 configuration/interface/endpoint descriptor register 10 USBF 1164 UF0CIE11 UF0 co
PAGE 1488
V850ES/JG3-H, V850ES/JH3-H APPENDIX C REGISTER INDEX (30/37) Symbol Name Unit Page UF0CIE46 UF0 configuration/interface/endpoint descriptor register 46 USBF 1164 UF0CIE47 UF0 configuration/interface/endpoint descriptor register 47 USBF 1164 UF0CIE48 UF0 configuration/interface/endpoint descriptor register 48 USBF 1164 UF0CIE49 UF0 configuration/interface/endpoint descriptor register 49 USBF 1164 UF0CIE50 UF0 configuration/interface/endpoint descriptor register 50 USBF 1164 UF0CIE51
PAGE 1489
V850ES/JG3-H, V850ES/JH3-H APPENDIX C REGISTER INDEX (31/37) Symbol Name Unit Page UF0CIE86 UF0 configuration/interface/endpoint descriptor register 86 USBF 1164 UF0CIE87 UF0 configuration/interface/endpoint descriptor register 87 USBF 1164 UF0CIE88 UF0 configuration/interface/endpoint descriptor register 88 USBF 1164 UF0CIE89 UF0 configuration/interface/endpoint descriptor register 89 USBF 1164 UF0CIE90 UF0 configuration/interface/endpoint descriptor register 90 USBF 1164 UF0CIE91
PAGE 1490
V850ES/JG3-H, V850ES/JH3-H APPENDIX C REGISTER INDEX (32/37) Symbol Name Unit Page UF0CIE126 UF0 configuration/interface/endpoint descriptor register 126 USBF 1164 UF0CIE127 UF0 configuration/interface/endpoint descriptor register 127 USBF 1164 UF0CIE128 UF0 configuration/interface/endpoint descriptor register 128 USBF 1164 UF0CIE129 UF0 configuration/interface/endpoint descriptor register 129 USBF 1164 UF0CIE130 UF0 configuration/interface/endpoint descriptor register 130 USBF 1164
PAGE 1491
V850ES/JG3-H, V850ES/JH3-H APPENDIX C REGISTER INDEX (33/37) Symbol Name Unit Page UF0CIE166 UF0 configuration/interface/endpoint descriptor register 166 USBF 1164 UF0CIE167 UF0 configuration/interface/endpoint descriptor register 167 USBF 1164 UF0CIE168 UF0 configuration/interface/endpoint descriptor register 168 USBF 1164 UF0CIE169 UF0 configuration/interface/endpoint descriptor register 169 USBF 1164 UF0CIE170 UF0 configuration/interface/endpoint descriptor register 170 USBF 1164
PAGE 1492
V850ES/JG3-H, V850ES/JH3-H APPENDIX C REGISTER INDEX (34/37) Symbol Name Unit Page UF0CIE206 UF0 configuration/interface/endpoint descriptor register 206 USBF 1164 UF0CIE207 UF0 configuration/interface/endpoint descriptor register 207 USBF 1164 UF0CIE208 UF0 configuration/interface/endpoint descriptor register 208 USBF 1164 UF0CIE209 UF0 configuration/interface/endpoint descriptor register 209 USBF 1164 UF0CIE210 UF0 configuration/interface/endpoint descriptor register 210 USBF 1164
PAGE 1493
V850ES/JG3-H, V850ES/JH3-H APPENDIX C REGISTER INDEX (35/37) Symbol Name Unit Page UF0CIE246 UF0 configuration/interface/endpoint descriptor register 246 USBF 1164 UF0CIE247 UF0 configuration/interface/endpoint descriptor register 247 USBF 1164 UF0CIE248 UF0 configuration/interface/endpoint descriptor register 248 USBF 1164 UF0CIE249 UF0 configuration/interface/endpoint descriptor register 249 USBF 1164 UF0CIE250 UF0 configuration/interface/endpoint descriptor register 250 USBF 1164
PAGE 1494
V850ES/JG3-H, V850ES/JH3-H APPENDIX C REGISTER INDEX (36/37) Symbol Name Unit Page UF0E0ST UF0 EP0 setup register USBF 1130 UF0E0W UF0 EP0 write register USBF 1132 UF0E1DC1 EP1 DMA control register 1 USBF 1170 UF0E1DC2 EP1 DMA control register 2 USBF 1172 UF0E1IM UF0 endpoint 1 interface mapping register USBF 1123 UF0E1SL UF0 EP1 status register L USBF 1153 UF0E2DC1 EP2 DMA control register 1 USBF 1170 UF0E2DC2 EP2 DMA control register 2 USBF 1172 UF0E2IM UF0 endpoint
PAGE 1495
V850ES/JG3-H, V850ES/JH3-H APPENDIX C REGISTER INDEX (37/37) Symbol Name Unit Page UF0IF2 UF0 interface 2 register USBF 1161 UF0IF3 UF0 interface 3 register USBF 1161 UF0IF4 UF0 interface 4 register USBF 1161 UF0IM0 UF0 INT mask 0 register USBF 1099 UF0IM1 UF0 INT mask 1 register USBF 1100 UF0IM2 UF0 INT mask 2 register USBF 1101 UF0IM3 UF0 INT mask 3 register USBF 1102 UF0IM4 UF0 INT mask 4 register USBF 1103 UF0INT1 UF0 interrupt 1 register USBF 1149 UF0IS0 UF0 I
PAGE 1496
V850ES/JG3-H, V850ES/JH3-H APPENDIX D INSTRUCTION SET LIST APPENDIX D INSTRUCTION SET LIST D.1 Conventions (1) Register symbols used to describe operands Register Symbol Explanation reg1 General-purpose registers: Used as source registers. reg2 General-purpose registers: Used mainly as destination registers. Also used as source register in some instructions. reg3 General-purpose registers: Used mainly to store the remainders of division results and the higher 32 bits of multiplication results.
PAGE 1497
V850ES/JG3-H, V850ES/JH3-H APPENDIX D INSTRUCTION SET LIST (3) Register symbols used in operations Register Symbol Explanation ← Input for GR [ ] General-purpose register SR [ ] System register zero-extend (n) Expand n with zeros until word length. sign-extend (n) Expand n with signs until word length. load-memory (a, b) Read size b data from address a. store-memory (a, b, c) Write data b into address a in size c. load-memory-bit (a, b) Read bit b of address a.
PAGE 1498
V850ES/JG3-H, V850ES/JH3-H APPENDIX D INSTRUCTION SET LIST (5) Register symbols used in flag operations Identifier Explanation (Blank) No change 0 Clear to 0 X Set or cleared in accordance with the results. R Previously saved values are restored.
PAGE 1499
V850ES/JG3-H, V850ES/JH3-H D.
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V850ES/JG3-H, V850ES/JH3-H APPENDIX D INSTRUCTION SET LIST (2/6) Mnemonic Operand Opcode Operation Execution Flags Clock DBTRAP 1111100001000000 DBPC←PC+2 (restored PC) i r l 3 3 3 1 1 1 CY OV S Z SAT DBPSW←PSW PSW.NP←1 PSW.EP←1 PSW.ID←1 PC←00000060H DI 0000011111100000 PSW.
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V850ES/JG3-H, V850ES/JH3-H APPENDIX D INSTRUCTION SET LIST (3/6) Mnemonic Operand Opcode Operation Execution Flags Clock LD.H disp16[reg1],reg2 rrrrr111001RRRRR adr←GR[reg1]+sign-extend(disp16) ddddddddddddddd0 GR[reg2]←sign-extend(Load-memory(adr,Halfword)) i r l 1 1 Note CY OV S Z SAT 11 Note 8 LDSR reg2,regID rrrrr111111RRRRR SR[regID]←GR[reg2] 0000000000100000 Other than regID = PSW 1 1 1 regID = PSW 1 1 1 1 1 Note × × × × 0 × × × Note 12 LD.
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V850ES/JG3-H, V850ES/JH3-H APPENDIX D INSTRUCTION SET LIST (4/6) Mnemonic Operand Opcode Operation Execution Flags Clock i r l CY OV S Z SAT OR reg1,reg2 r r rr r0 01 00 0 RRRRR GR[reg2]←GR[reg2]OR GR[reg1] 1 1 1 0 × × ORI imm16,reg1,reg2 r r rr r1 10 10 0 RRRRR GR[reg2]←GR[reg1]OR zero-extend(imm16) 1 1 1 0 × × i i i i i i i i i i i i i i i i PREPARE list12,imm5 0000011110iiiiiL Store-memory(sp–4,GR[reg in list12],Word) LLLLLLLLLLL00001 sp←sp–4 n+1 n+1 n+1 Note 4 Note 4
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V850ES/JG3-H, V850ES/JH3-H APPENDIX D INSTRUCTION SET LIST (5/6) Mnemonic Operand Opcode Operation Execution Flags Clock SET1 bit#3,disp16[reg1] 00bbb111110RRRRR adr←GR[reg1]+sign-extend(disp16) dddddddddddddddd Z flag←Not (Load-memory-bit(adr,bit#3)) i r l 3 3 3 CY OV S Z SAT × Note 3 Note 3 Note 3 Store-memory-bit(adr,bit#3,1) reg2,[reg1] r r rr r1 11 11 1 RRRRR adr←GR[reg1] 0000000011100000 Z flag←Not(Load-memory-bit(adr,reg2)) 3 3 × 3 Note 3 Note 3 Note 3 Store-memory-bit
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V850ES/JG3-H, V850ES/JH3-H APPENDIX D INSTRUCTION SET LIST (6/6) Mnemonic Operand Opcode Operation Execution Flags Clock i r l CY OV S Z SAT SUB reg1,reg2 r r rr r0 01 10 1 RRRRR GR[reg2]←GR[reg2]–GR[reg1] 1 1 1 × × × × SUBR reg1,reg2 r r rr r0 01 10 0 RRRRR GR[reg2]←GR[reg1]–GR[reg2] 1 1 1 × × × × SWITCH reg1 00000000010RRRRR adr←(PC+2) + (GR [reg1] logically shift left by 1) 5 5 5 1 1 1 1 1 1 3 3 3 1 1 1 0 × × 3 3 3 PC←(PC+2) + (sign-extend (Load-
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V850ES/JG3-H, V850ES/JH3-H APPENDIX D INSTRUCTION SET LIST Notes 12. In this instruction, for convenience of mnemonic description, the source register is made reg2, but the reg1 field is used in the opcode. Therefore, the meaning of register specification in the mnemonic description and in the opcode differs from other instructions. rrrrr = regID specification RRRRR = reg2 specification 13. i i i i i : Lower 5 bits of imm9. IIII: Higher 4 bits of imm9. 14.
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V850ES/JG3-H, V850ES/JH3-H APPENDIX E REVISION HISTORY APPENDIX E REVISION HISTORY E.1 Major Revisions in This Edition Page p.34 Description Modification of 2.1 (1) Port pins pp.38 to 46 Modification of 2.1 (2) Non-Port pins p.101 Addition of Caution to Figure 4-1. Port Configuration Diagram (V850ES/JG3-H) p.101 Addition of Caution to Figure 4-2. Port Configuration Diagram (V850ES/JH3-H) p.816 Modification of Figure 19-3. UARTC1 and I2C02 Mode Switch Settings R01UH0042EJ0500 Rev.5.
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V850ES/JG3-H, V850ES/JH3-H E.2 APPENDIX E REVISION HISTORY Revision History of Preceding Editions Here is the revision history of the preceding editions. Chapter indicates the chapter of each edition. (1/4) Edition 3rd Description Addition of Note to 5.5.1(1) Data wait control register 0 (DWC0) Addition of Note to 5.5.4(1) Address wait control register (AWC) Chapter CHAPTER 5 BUS CONTROL FUNCTIONS Addition of Note to 5.
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V850ES/JG3-H, V850ES/JH3-H APPENDIX E REVISION HISTORY (2/4) Edition 2nd Description Chapter Modification of 3.4.4 (2) (d) Data-only RAM (8 KB) CHAPTER 3 Addition of Caution to 3.4.4 (2) (d) Data-only RAM (8 KB) CPU FUNCTION Modification of Figure 3-10. Data only RAM (8 KB) Modification of 3.4.4 (4) External memory area Modification of 3.4.6 Peripheral I/O registers Modification of Figure 7-23. (d) TAAn I/O control register 2 (TAAnIOC2) CHAPTER 7 Modification of Figure 7-27.
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V850ES/JG3-H, V850ES/JH3-H APPENDIX E REVISION HISTORY (3/4) Edition 2nd Description Chapter Modification of 3.4.4 (2) (d) Data-only RAM (8 KB) CHAPTER 3 Addition of Caution to 3.4.4 (2) (d) Data-only RAM (8 KB) CPU FUNCTION Modification of Figure 3-10. Data only RAM (8 KB) Modification of 3.4.4 (4) External memory area Modification of 3.4.6 Peripheral I/O registers Modification of Figure 7-23. (d) TAAn I/O control register 2 (TAAnIOC2) CHAPTER 7 Modification of Figure 7-27.
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V850ES/JG3-H, V850ES/JH3-H APPENDIX E REVISION HISTORY (4/4) Edition 3rd Description Chapter Modification of 4.3.3 (6)Port 2 alternate function specifications CHAPTER 4 Modification of 4.3.9 Port 9 function control register (PFC9) PORT FUNCTION Modification of 4.3.9 Port 9 function control expansion register (PFCE9) Modification of Table 4-20. Using Port Pin as Alternate-Function Pin Modification of Figure 12-1. Block Diagram of Real-Time Counter CHAPTER 12 Modification of 12.2.
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V850ES/JG3-H, V850ES/JH3-H User’s Manual: Hardware Publication Date: Rev.4.00 Rev.5.
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V850ES/JG3-H, V850ES/JH3-H R01UH0042EJ0500