Datasheet

4.3.10 Port DH ....................................................................................................................................101
4.3.11 Port DL.....................................................................................................................................103
4.4 Block Diagrams..................................................................................................................... 106
4.5 Port Register Settings When Alternate Function Is Used ................................................ 136
CHAPTER 5 BUS CONTROL FUNCTION .......................................................................................... 149
5.1 Features................................................................................................................................. 149
5.2 Bus Control Pins................................................................................................................... 150
5.2.1 Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed...............150
5.2.2 Pin status in each operation mode...........................................................................................150
5.3 Memory Block Function....................................................................................................... 151
5.4 External Bus Interface Mode Control Function................................................................. 152
5.5 Bus Access ........................................................................................................................... 153
5.5.1 Number of clocks for access....................................................................................................153
5.5.2 Bus size setting function ..........................................................................................................153
5.5.3 Access by bus size ..................................................................................................................154
5.6 Wait Function ........................................................................................................................ 161
5.6.1 Programmable wait function.....................................................................................................161
5.6.2 External wait function...............................................................................................................162
5.6.3 Relationship between programmable wait and external wait ...................................................163
5.6.4 Programmable address wait function.......................................................................................164
5.7 Idle State Insertion Function ............................................................................................... 165
5.8 Bus Hold Function................................................................................................................ 166
5.8.1 Functional outline.....................................................................................................................166
5.8.2 Bus hold procedure..................................................................................................................167
5.8.3 Operation in power save mode ................................................................................................167
5.9 Bus Priority ........................................................................................................................... 168
5.10 Bus Timing ............................................................................................................................ 169
CHAPTER 6 CLOCK GENERATION FUNCTION .............................................................................. 175
6.1 Overview................................................................................................................................ 175
6.2 Configuration ........................................................................................................................ 176
6.3 Registers ............................................................................................................................... 178
6.4 Operation............................................................................................................................... 183
6.4.1 Operation of each clock ...........................................................................................................183
6.4.2 Clock output function ...............................................................................................................183
6.5 PLL Function......................................................................................................................... 184
6.5.1 Overview..................................................................................................................................184
6.5.2 Registers..................................................................................................................................184
6.5.3 Usage ......................................................................................................................................187
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) ................................................................ 188
7.1 Overview................................................................................................................................ 188
7.2 Functions............................................................................................................................... 188
7.3 Configuration ........................................................................................................................ 189
7.4 Registers ............................................................................................................................... 191
7.5 Operation............................................................................................................................... 203
7.5.1 Interval timer mode (TPnMD2 to TPnMD0 bits = 000) .............................................................204
7.5.2 External event count mode (TPnMD2 to TPnMD0 bits = 001) .................................................214
7.5.3 External trigger pulse output mode (TPnMD2 to TPnMD0 bits = 010) .....................................222