Datasheet

V850ES/JG3 APPENDIX E LIST OF CAUTIONS
R01UH0015EJ0300 Rev.3.00 Page 868 of 870
Sep 30, 2010
(35/36)
Chapter
Classification
Function Details of
Function
Cautions Page
When using the subclock oscillator, wire as follows in the area enclosed by the
broken lines in the above figures to avoid an adverse effect from wiring
capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating
current flows.
• Always make the ground point of the oscillator capacitor the same potential as
V
SS.
• Do not ground the capacitor to a ground pattern through which a high current
flows.
• Do not fetch signals from the oscillator.
p. 770
The subclock oscillator is designed as a low-amplitude circuit for reducing power
consumption, and is more prone to malfunction due to noise than the main clock
oscillator.
Particular care is therefore required with the wiring method when the subclock is
used.
p. 770
Subclock
oscillator
characteristics
For the resonator selection and oscillator constant, customers are requested to
either evaluate the oscillation themselves or apply to the resonator manufacturer
for evaluation.
p. 770
Data retention
characteristics
Shifting to STOP mode and restoring from STOP mode must be performed within
the rated operating range.
p. 775
Hard
AC
characteristics
If the load capacitance exceeds 50 pF due to the circuit configuration, bring the
load capacitance of the device to 50 pF or less by inserting a buffer or by some
other means.
p. 776
Bus timing
(multiplexed
bus mode)
When operating at fXX > 20 MHz, be sure to insert address hold waits and address
setup waits.
p. 778
When operating at fXX > 20 MHz, be sure to insert address hold waits, address
setup waits, and data waits.
p. 783Bus timing
(separate bus
mode)
The address may be changed during the low-level period of the RD pin. To avoid
the address change, insert an address wait.
p. 783
At the start condition, the first clock pulse is generated after the hold time. p. 794
The system requires a minimum of 300 ns hold time internally for the SDA0n
signal (at V
IHmin. of SCL0n signal) in order to occupy the undefined area at the
falling edge of SCL0n.
p. 794
If the system does not extend the SCL0n signal low hold time (tLOW), only the
maximum data hold time (t
HD:DAT) needs to be satisfied.
p. 794
I
2
C bus mode
The high-speed mode I
2
C bus can be used in the normal-mode I
2
C bus system. In
this case, set the high-speed mode I
2
C bus so that it meets the following
conditions.
• If the system does not extend the SCL0n signal’s low state hold time:
t
SU:DAT ≥ 250 ns
• If the system extends the SCL0n signal’s low state hold time:
Transmit the following data bit to the SDA0n line prior to the SCL0n line release
(t
Rmax. + tSU:DAT = 1,000 + 250 = 1,250 ns: Normal mode I
2
C bus specification).
p. 794
Chapter 29
Soft
Electrical
specifica-
tions
A/D converter Do not set (read/write) alternate-function ports during A/D conversion; otherwise
the conversion resolution may be degraded.
p. 795