Datasheet

V850ES/JG3 APPENDIX E LIST OF CAUTIONS
R01UH0015EJ0300 Rev.3.00 Page 866 of 870
Sep 30, 2010
(33/36)
Chapter
Classification
Function Details of
Function
Cautions Page
Wire the FLMD1 pin as shown below, or connect it to GND on board via a pull-
down resistor.
p. 733
Supply a clock by creating an oscillator on the flash writing adapter (enclosed by
the broken lines).
p. 733
FA-144GJ-UEN-A
Do not input a high level to the DRST pin. p. 733
Selection of
communication
mode
When UARTA0 is selected, the receive clock is calculated based on the reset
command sent from the dedicated flash programmer after receiving the FLMD0
pulse.
p. 735
FLMD1 pin If the VDD signal is input to the FLMD1 pin from another device during on-board
writing and immediately after reset, isolate this signal.
p. 737
Chapter 27
Hard
Flash
memory
FLMD0 pin Make sure that the FLMD0 pin is at 0 V when reset is released.
p. 744
When using the DDI, DDO, DCK, and DMS pins not as on-chip debug pins but as
port pins after external reset, any of the following actions must be taken.
• Input a low level to the P05/INTP2/DRST pin.
• Set the OCDM0 bit. In this case, take the following actions.
<1> Clear the OCDM0 bit to 0.
<2> Fix the P05/INTP2/DRST pin to low level until <1> is completed.
p. 750
Hard, soft
OCDM register
The DRST pin has an on-chip pull-down resistor. This resistor is disconnected
when the OCDM0 flag is cleared to 0.
p. 750
If a reset signal is input (from the target system or a reset signal from an internal
reset source) during RUN (program execution), the break function may
malfunction.
p. 751
Even if the reset signal is masked by the mask function, the I/O buffer (port pin)
may be reset if a reset signal is input from a pin.
p. 751
Soft
Pin reset during a break is masked and the CPU and peripheral I/O are not reset.
If pin reset or internal reset is generated as soon as the flash memory is rewritten
by DMM or read by the RAM monitor function while the user program is being
executed, the CPU and peripheral I/O may not be correctly reset.
p. 751
Cautions (DUC)
In the on-chip debug mode, the DDO pin is forcibly set to the high-level output.
p. 751
Hard
Do not mount a device that was used for debugging on a mass-produced product,
because the flash memory was rewritten during debugging and the number of
rewrites of the flash memory cannot be guaranteed.
Moreover, do not embed the debug monitor program into mass-produced
products.
p. 760
Forced breaks cannot be executed if one of the following conditions is satisfied.
• Interrupts are disabled (DI)
• Interrupts issued for the serial interface, which is used for communication
between MINICUBE2 and the target device, are masked
• Standby mode is entered while standby release by a maskable interrupt is
prohibited
• Mode for communication between MINICUBE2 and the target device is
UARTA0, and the main clock has been stopped
p. 760
Chapter 28
Soft
On-chip
debug
function
Cautions (other
than DUC)
The pseudo RRM function and DMM function do not operate if one of the
following conditions is satisfied.
• Interrupts are disabled (DI)
• Interrupts issued for the serial interface, which is used for communication
between MINICUBE2 and the target device, are masked
• Standby mode is entered while standby release by a maskable interrupt is
prohibited
• Mode for communication between MINICUBE2 and the target device is
UARTA0, and the main clock has been stopped
• Mode for communication between MINICUBE2 and the target device is
UARTA0, and a clock different from the one specified in the debugger is used
for communication
p. 761