Datasheet

V850ES/JG3 APPENDIX E LIST OF CAUTIONS
R01UH0015EJ0300 Rev.3.00 Page 865 of 870
Sep 30, 2010
(32/36)
Chapter
Classification
Function Details of
Function
Cautions Page
Chapter 22
Hard, Soft
Reset
function
Hardware status
on RESET pin
input
The OCDM register is initialized by the RESET pin input. Therefore, note with
caution that, if a high level is input to the P05/DRST pin after a reset release
before the OCDM.OCDM0 bit is cleared, the on-chip debug mode is entered. For
details, see CHAPTER 4 PORT FUNCTIONS.
p. 695
Once the CLME bit has been set to 1, it cannot be cleared to 0 by any means
other than reset.
p. 703
CLM register
When a reset by the clock monitor occurs, the CLME bit is cleared to 0 and the
RESF.CLMRF bit is set to 1.
p. 703
The internal oscillator can be stopped by setting the RCM.RSTOP bit to 1.
p. 704
The clock monitor is stopped while the internal oscillator is stopped.
p. 704
Chapter 23
Soft
Clock
monitor
Internal
oscillator
The internal oscillator cannot be stopped by software.
p. 704
When the LVION and LVIMD bits to 1, the low-voltage detector cannot be
stopped until the reset request due to other than the low-voltage detection is
generated.
p. 708
When the LVION bit is set to 1, the comparator in the LVI circuit starts operating.
Wait 0.2 ms or longer by software before checking the voltage at the LVIF bit after
the LVION bit is set.
p. 708
LVIM register
Be sure to clear bits 6 to 2 to “0”.
p. 708
This register cannot be written until a reset request due to something other than
low-voltage detection is generated after the LVIM.LVION and LVIM.LVIMD bits
are set to 1.
p. 709
LVIS register
Be sure to clear bits 7 to 1 to “0”.
p. 709
To use for
internal reset
signal
If the LVIMD bit is set to 1, the contents of the LVIM and LVIS registers cannot be
changed until a reset request other than LVI is generated.
p. 710
To use for
interrupt
When the INTLVI signal is generated, confirm, using the LVIM/LVIF bit, whether
the INTLVI signal is generated due to a supply voltage drop or rise across the
detected voltage.
p. 711
Chapter 24
Soft
Low-
voltage
detector
(LVI)
PEMU1 register This bit is not automatically cleared.
p. 713
Chapter 25
Hard
CRC
function
CRCD register Accessing the CRCD register is prohibited in the following statuses. For details,
refer to 3.4.9 (2) Accessing specific on-chip peripheral I/O registers.
• When the CPU operates with the subclock and the main clock oscillation is
stopped
• When the CPU operates with the internal oscillation clock
p. 715
Chapter 26
Hard
Regulator Regulator Use the regulator with a setting of VDD = EVDD = AVREF0 = AVREF1.
p. 719
pp.
FLMD1 pin Connect the FLMD1 pin to the flash programmer or connect to a GND via a pull-
down resistor on the board.
727 to 729
Wire these pins as shown in Figure 27-6, or connect then to GND via pull-down
resistor on board.
p. 729
PG-FP4
Clock cannot be supplied via the CLK pin of the flash programmer. Create an
oscillator on board and supply the clock.
p. 729
pp.
Be sure to connect the REGC pin to GND via a 4.7 μ F (recommended value)
capacitor.
730, 731
pp.
Chapter 27
Hard
Flash
memory
FA-144GJ-UEN-A
A clock cannot be supplied from the CLK pin of the flash programmer. Create an
oscillator on the board and supply the clock from that oscillator.
730, 731