Datasheet

V850ES/JG3 APPENDIX E LIST OF CAUTIONS
R01UH0015EJ0300 Rev.3.00 Page 864 of 870
Sep 30, 2010
(31/36)
Chapter
Classification
Function Details of
Function
Cautions Page
Releasing
IDLE2 mode
The interrupt request signal that is disabled by setting the PSC.NMI1M,
PSC.NMI0M, and PSC.INTM bits to 1 becomes invalid and IDLE2 mode is not
released.
p. 682
Insert five or more NOP instructions after the instruction that stores data in the
PSC register to set the STOP mode.
p. 685
STOP mode
If the STOP mode is set while an unmasked interrupt request signal is being held
pending, the STOP mode is released immediately by the pending interrupt
request.
p. 685
Releasing
STOP mode
The interrupt request that is disabled by setting the PSC.NMI1M, PSC.NMI0M,
and PSC.INTM bits to 1 becomes invalid and STOP mode is not released.
p. 685
When manipulating the CK3 bit, do not change the set values of the PCC.CK2 to
PCC.CK0 bits (using a bit manipulation instruction to manipulate the bit is
recommended). For details of the PCC register, see 6.3 (1) Processor clock
control register (PCC).
p. 689
Subclock
operation mode
If the following conditions are not satisfied, change the CK2 to CK0 bits so that
the conditions are satisfied and set the subclock operation mode.
Internal system clock (f
CLK) > Subclock (fXT = 32.768 kHz) × 4
p. 689
When manipulating the CK3 bit, do not change the set values of the CK2 to CK0
bits (using a bit manipulation instruction to manipulate the bit is recommended).
For details of the PCC register, see 6.3 (1) Processor clock control register
(PCC).
p. 689
Be sure to stop the PLL (PLLCTL.PLLON bit = 0) before stopping the main clock.
p. 690
Releasing
subclock
operation mode
When the CPU is operating on the subclock and main clock oscillation is stopped,
accessing a register in which a wait occurs is disabled. If a wait is generated, it
can be released only by reset (see 3.4.8 (2)).
p. 690
Following the store instruction to the PSC register to set the sub-IDLE mode,
insert the five or more NOP instructions.
p. 691
Sub-IDLE mode
If the sub-IDLE mode is set while an unmasked interrupt request signal is being
held pending, the sub-IDLE mode is then released immediately by the pending
interrupt request.
p. 691
The interrupt request signal that is disabled by setting the PSC.NMI1M,
PSC.NMI0M, and PSC.INTM bits to 1 becomes invalid and sub-IDLE mode is not
released.
p. 691
Releasing sub-
IDLE mode
When the sub-IDLE mode is released, 12 cycles of the subclock (about 366
μ s)
elapse from when the interrupt request signal that releases the sub-IDLE mode is
generated to when the mode is released.
p. 691
Be sure to stop the PLL (PLLCTL.PLLON bit = 0) before stopping the main clock.
p. 692
Chapter 21
Soft
Standby
function
Operating
status in sub-
IDLE mode
To realize low power consumption, stop the A/D and D/A converters before
shifting to the sub-IDLE mode.
p. 692
Emergency
operation mode
In emergency operation mode, do not access on-chip peripheral I/O registers
other than registers used for interrupts, port function, WDT2, or timer M, each of
which can operate with the internal oscillation clock. In addition, operation of
CSIB0 to CSIB4 and UARTA0 using the externally input clock is also prohibited in
this mode.
p. 693
Reset function An LVI circuit internal reset does not reset the LVI circuit.
p. 693
Soft
RESF register Only “0” can be written to each bit of this register. If writing “0” conflicts with
setting the flag (occurrence of reset), setting the flag takes precedence.
p. 694
p. 695
Chapter 22
Hard
Reset
function
Hardware status
on RESET pin
input
When the power is turned on, the following pin may output an undefined level
temporarily, even during reset.
• P53/SIB2/KR3/TIQ00/TOQ00/RTP03/DDO pin