Datasheet

V850ES/JG3 APPENDIX E LIST OF CAUTIONS
R01UH0015EJ0300 Rev.3.00 Page 863 of 870
Sep 30, 2010
(30/36)
Chapter
Classification
Function Details of
Function
Cautions Page
Rewrite the KRM register after once clearing the KRM register to 00H. p. 672KRM register
If the KRM register is changed, an interrupt request signal (INTKR) may be
generated. To prevent this, change the KRM register after disabling interrupts (DI)
or masking, then clear the interrupt request flag (KRIC.KRIF bit) to 0, and enable
interrupts (EI) or clear the mask.
p. 672
KR0 to KR7
pins
If a low level is input to any of the KR0 to KR7 pins, the INTKR signal is not
generated even if the falling edge of another pin is input.
p. 672
RXDA1 pin
KR7 pin
The RXDA1 and KR7 pins must not be used at the same time. To use the RXDA1
pin, do not use the KR7 pin.
To use the KR7 pin, do not use the RXDA1 pin (it is recommended to set the
PFC91 bit to 1 and clear PFCE91 bit to 0).
p. 672
Chapter 20
Soft
Key
interrupt
function
Use the key
interrupt
function
To use the key interrupt function, be sure to set the port pin to the key return pin
and then enable the operation with the KRM register. To switch from the key
return pin to the port pin, disable the operation with the KRM register and then set
the port pin.
p. 672
Before setting the IDLE1, IDLE2, STOP, or sub-IDLE mode, set the PSMR.PSM1
and PSMR.PSM0 bits and then set the STP bit.
p. 675
Settings of the NMI1M, NMI0M, and INTM bits are invalid when HALT mode is
released.
p. 675
PSC register
If the NMI1M, NMI0M, or INTM bit is set to 1 at the same time the STP bit is set to
1, the setting of NMI1M, NMI0M, or INTM bit becomes invalid. If there is an
unmasked interrupt request signal being held pending when the
IDLE1/IDLE2/STOP mode is set, set the bit corresponding to the interrupt request
signal (NMI1M, NMI0M, or INTM) to 1, and then set the STP bit to 1.
p. 675
Be sure to clear bits 2 to 7 to “0”.
p. 676
PSMR register
The PSM0 and PSM1 bits are valid only when the PSC.STP bit is 1.
p. 676
The wait time following release of the STOP mode does not include the time until
the clock oscillation starts (“a” in the figure below) following release of the STOP
mode, regardless of whether the STOP mode is released by reset or the
occurrence of an interrupt request signal.
p. 677
Be sure to clear bits 3 to 7 to “0”.
p. 677
OSTS register
The oscillation stabilization time following reset release is 2
16
/fX (because the initial
value of the OSTS register = 06H).
p. 677
Insert five or more NOP instructions after the HALT instruction.
p. 678
HALT mode
If the HALT instruction is executed while an unmasked interrupt request signal is
being held pending, the status shifts to HALT mode, but the HALT mode is then
released immediately by the pending interrupt request.
p. 678
Insert five or more NOP instructions after the instruction that stores data in the
PSC register to set the IDLE1 mode.
p. 680
IDLE1 mode
If the IDLE1 mode is set while an unmasked interrupt request signal is being held
pending, the IDLE1 mode is released immediately by the pending interrupt
request.
p. 680
Releasing
IDLE1 mode
An interrupt request signal that is disabled by setting the PSC.NMI1M,
PSC.NMI0M, and PSC.INTM bits to 1 becomes invalid and IDLE1 mode is not
released.
p. 680
Insert five or more NOP instructions after the instruction that stores data in the
PSC register to set the IDLE2 mode.
p. 682
Chapter 21
Soft
Standby
function
IDLE2 mode
If the IDLE2 mode is set while an unmasked interrupt request signal is being held
pending, the IDLE2 mode is released immediately by the pending interrupt
request.
p. 682