Datasheet

V850ES/JG3 APPENDIX E LIST OF CAUTIONS
R01UH0015EJ0300 Rev.3.00 Page 861 of 870
Sep 30, 2010
(28/36)
Chapter
Classification
Function Details of
Function
Cautions Page
DMA start factor Do not start two or more DMA channels with the same start factor. If two or more
channels are started with the same factor, DMA for which a channel has already
been set may be started or a DMA channel with a lower priority may be
acknowledged earlier than a DMA channel with a higher priority. The operation
cannot be guaranteed.
p. 633
Chapter 18
Soft
DMA
function
(DMA
controller)
Read values of
DSAn and
DDAn registers
Values in the middle of updating may be read from the DSAn and DDAn registers
during DMA transfer (n = 0 to 3).
For example, if the DSAnH register and then the DSAnL register are read when
the DMA transfer source address (DSAn register) is 0000FFFFH and the count
direction is incremental (DADCn.SAD1 and DADCn.SAD0 bits = 00), the value of
the DSAn register differs as follows, depending on whether DMA transfer is
executed immediately after the DSAnH register is read.
(a) If DMA transfer does not occur while DSAn register is read
<1> Read value of DSAnH register: DSAnH = 0000H
<2> Read value of DSAnL register: DSAnL = FFFFH
(b) If DMA transfer occurs while DSAn register is read
<1> Read value of DSAnH register: DSAnH = 0000H
<2> Occurrence of DMA transfer
<3> Incrementing DSAn register: DSAn = 00100000H
<4> Read value of DSAnL register: DSAnL = 0000H
p. 634
For the non-maskable interrupt servicing executed by the non-maskable interrupt
request signal (INTWDT2), see 19.2.2 (2) From INTWDT2 signal.
p. 639Non-maskable
interrupts
When the EP and NP bits are changed by the LDSR instruction during non-
maskable interrupt servicing, in order to restore the PC and PSW correctly during
recovery by the RETI instruction, it is necessary to set the EP bit back to 0 and
the NP bit back to 1 using the LDSR instruction immediately before the RETI
instruction.
p. 642
Maskable
interrupt
When the EP and NP bits are changed by the LDSR instruction during maskable
interrupt servicing, in order to restore the PC and PSW correctly during recovery
by the RETI instruction, it is necessary to set the EP bit back to 0 and the NP bit
back to 0 using the LDSR instruction immediately before the RETI instruction.
p. 646
Multiple
interrupt
To perform multiple interrupt servicing, the values of the EIPC and EIPSW
registers must be saved before executing the EI instruction. When returning from
multiple interrupt servicing, restore the values of EIPC and EIPSW after executing
the DI instruction.
pp.
648 to
650
Disable interrupts (DI) or mask the interrupt to read the xxICn.xxIFn bit. If the
xxIFn bit is read while interrupts are enabled (EI) or while the interrupt is
unmasked, the correct value may not be read when acknowledging an interrupt
and reading the bit conflict.
p. 651Interrupt control
register
The flag xxlFn is reset automatically by the hardware if an interrupt request signal
is acknowledged.
p. 651
The device file defines the xxICn.xxMKn bit as a reserved word. If a bit is
manipulated using the name of xxMKn, the contents of the xxICn register, instead
of the IMRm register, are rewritten (as a result, the contents of the IMRm register
are also rewritten).
p. 653
To read bits 8 to 15 of the IMR0 to IMR3 registers in 8-bit or 1-bit units, specify
them as bits 0 to 7 of IMR0H to IMR3H registers.
p. 653
Chapter 19
Soft
Interrupt/
exception
processing
function
IMR0 to IMR3
registers
Set bits 7 to 15 of the IMR3 register to 1. If the setting of these bits is changed,
the operation is not guaranteed.
p. 653