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ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 100 32-Bit 32 MHz I/O number 84

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V850ES/JG3 APPENDIX E LIST OF CAUTIONS

R01UH0015EJ0300 Rev.3.00 Page 860 of 870

Sep 30, 2010

(27/36)

Chapter

Classification

Function Details of

Function

Cautions Page

DMA transfer

initialization

procedure

(setting

DCHCn.INITn

bit to 1)

<4> Again, clear the Enn bit of the channel to be forcibly terminated.

If the target of transfer for the channel to be forcibly terminated (transfer

source/destination) is the internal RAM, execute this operation once

more.

<5> Copy the initial number of transfers of the channel to be forcibly

terminated to a general-purpose register.

<6> Set the INITn bit of the channel to be forcibly terminated to 1.

<7> Read the value of the DBCn register of the channel to be forcibly

terminated, and compare it with the value copied in <5>. If the two values

do not match, repeat operations <6> and <7>.

p. 632

Procedure of

temporarily

stopping DMA

transfer

(clearing Enn

bit)

Stop and resume the DMA transfer under execution using the following

procedure.

<1> Suppress a transfer request from the DMA request source (stop the operation

of the on-chip peripheral I/O).

<2> Check the DMA transfer request is not held pending, by using the DFn bit

(check if the DFn bit = 0).

If a request is pending, wait until execution of the pending DMA transfer

request is completed.

<3> If it has been confirmed that no DMA transfer request is held pending, clear

the Enn bit to 0 (this operation stops DMA transfer).

<4> Set the Enn bit to 1 to resume DMA transfer.

<5> Resume the operation of the DMA request source that has been stopped

(start the operation of the onchip peripheral I/O).

p. 632

Memory

boundary

The operation is not guaranteed if the address of the transfer source or

destination exceeds the area of the DMA target (external memory, internal RAM,

or on-chip peripheral I/O) during DMA transfer.

p. 632

Transferring

misaligned data

DMA transfer of misaligned data with a 16-bit bus width is not supported.

If an odd address is specified as the transfer source or destination, the least

significant bit of the address is forcibly assumed to be 0.

p. 632

Bus arbitration

for CPU

Because the DMA controller has a higher priority bus mastership than the CPU, a

CPU access that takes place during DMA transfer is held pending until the DMA

transfer cycle is completed and the bus is released to the CPU.

However, the CPU can access the external memory, on-chip peripheral I/O, and

internal RAM to/from which DMA transfer is not being executed.

• The CPU can access the internal RAM when DMA transfer is being executed

between the external memory and on-chip peripheral I/O.

• The CPU can access the internal RAM and on-chip peripheral I/O when DMA

transfer is being executed between the external memory and external memory.

p. 633

Registers/bits

that must not be

rewritten during

DMA operation

Set the following registers at the following timing when a DMA operation is not

under execution.

[Registers]

• DSAnH, DSAnL, DDAnH, DDAnL, DBCn, and DADCn registers

• DTFRn.IFCn5 to DTFRn.IFCn0 bits

[Timing of setting]

• Period from after reset to start of the first DMA transfer

• Time after channel initialization to start of DMA transfer

• Period from after completion of DMA transfer (TCn bit = 1) to start of the next