Datasheet

V850ES/JG3 APPENDIX E LIST OF CAUTIONS
R01UH0015EJ0300 Rev.3.00 Page 858 of 870
Sep 30, 2010
(25/36)
Chapter
Classification
Function Details of
Function
Cautions Page
The TCn bit is read-only. p. 618
The INITn and STGn bits are write-only. p. 618
Be sure to clear bits 6 to 3 of the DCHCn register to 0. p. 618
DCHC0 to
DCHC3
registers
When DMA transfer is completed (when a terminal count is generated), the Enn
bit is cleared to 0 and then the TCn bit is set to 1. If the DCHCn register is read
while its bits are being updated, a value indicating “transfer not completed and
transfer is disabled” (TCn bit = 0 and Enn bit = 0) may be read.
p. 618
Do not set the DFn bit to 1 by software. Write 0 to this bit to clear a DMA transfer
request if an interrupt that is specified as the cause of starting DMA transfer
occurs while DMA transfer is disabled.
p. 619
Set the IFCn5 to IFCn0 bits at the following timing when DMA transfer is disabled
(DCHCn.Enn bit = 0).
• Period from after reset to start of first DMA transfer
• Period from after channel initialization by DCHCn.INITn bit to start of DMA
transfer
• Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of
the next DMA transfer
p. 619
An interrupt request that is generated in the standby mode (IDEL1, IDLE2, STOP,
or sub-IDLE mode) does not start the DMA transfer cycle (nor is the DFn bit set to
1).
p. 619
DTFR0 to
DTFR3
registers
If a DMA start factor is selected by the IFCn5 to IFCn0 bits, the DFn bit is set to 1
when an interrupt occurs from the selected on-chip peripheral I/O, regardless of
whether the DMA transfer is enabled or disabled. If DMA is enabled in this status,
DMA transfer is immediately started.
p. 619
Relationship
between
transfer targets
The operation is not guaranteed for combinations of transfer destination and
source marked with “ד in Table 18-2.
p. 621
Two start factors (software trigger and hardware trigger) cannot be used for one
DMA channel. If two start factors are simultaneously generated for one DMA
channel, only one of them is valid. The start factor that is valid cannot be
identified.
p. 624
A new transfer request that is generated after the preceding DMA transfer request
was generated or in the preceding DMA transfer cycle is ignored (cleared).
p. 624
Request by on-
chip peripheral
I/O
The transfer request interval of the same DMA channel varies depending on the
setting of bus wait in the DMA transfer cycle, the start status of the other
channels, or the external bus hold request. In particular, as described in Caution
2, a new transfer request that is generated for the same channel before the DMA
transfer cycle or during the DMA transfer cycle is ignored. Therefore, the transfer
request intervals for the same DMA channel must be sufficiently separated by the
system. When the software trigger is used, completion of the DMA transfer cycle
that was generated before can be checked by updating the DBCn register.
p. 624
Chapter 18
Soft
DMA
function
(DMA
controller)
Caution for
VSWC register
When using the DMAC, be sure to set an appropriate value, in accordance with
the operating frequency, to the VSWC register.
When the default value (77H) of the VSWC register is used, or if an inappropriate
value is set to the VSWC register, the operation is not correctly performed (for
details of the VSWC register, see 3.4.8 (1) (a) System wait control register
(VSWC)).
p. 630