Datasheet

V850ES/JG3 APPENDIX E LIST OF CAUTIONS
R01UH0015EJ0300 Rev.3.00 Page 857 of 870
Sep 30, 2010
(24/36)
Chapter
Classification
Function Details of
Function
Cautions Page
When the value of the DSAn register is read, two 16-bit registers, DSAnH and
DSAnL, are read. If reading and updating conflict, the value being updated may
be read (see 18.13 Cautions).
p. 614DSA0 to DSA3
registers
Following reset, set the DSAnH, DSAnL, DDAnH, DDAnL, and DBCn registers
before starting DMA transfer. If these registers are not set, the operation when
DMA transfer is started is not guaranteed.
p. 614
Be sure to clear bits 14 to 10 of the DDAnH register to 0. p. 615
Set the DDAnH and DDAnL registers at the following timing when DMA transfer is
disabled (DCHCn.Enn bit = 0).
• Period from after reset to start of first DMA transfer
• Period from after channel initialization by DCHCn.INITn bit to start of DMA
transfer
• Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of
the next DMA transfer
p. 615
When the value of the DDAn register is read, two 16-bit registers, DDAnH and
DDAnL, are read. If reading and updating conflict, a value being updated may be
read (see 18.13 Cautions).
p. 615
DDA0 to DDA3
registers
Following reset, set the DSAnH, DSAnL, DDAnH, DDAnL, and DBCn registers
before starting DMA transfer. If these registers are not set, the operation when
DMA transfer is started is not guaranteed.
p. 615
Set the DBCn register at the following timing when DMA transfer is disabled
(DCHCn.Enn bit = 0).
• Period from after reset to start of first DMA transfer
• Period from after channel initialization by DCHCn.INITn bit to start of DMA
transfer
• Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of
the next DMA transfer
p. 616DBC0 to DBC3
registers
Following reset, set the DSAnH, DSAnL, DDAnH, DDAnL, and DBCn registers
before starting DMA transfer. If these registers are not set, the operation when
DMA transfer is started is not guaranteed.
p. 616
Be sure to clear bits 15, 13 to 8, and 3 to 0 of the DADCn register to “0”. p. 617
Set the DADCn register at the following timing when DMA transfer is disabled
(DCHCn.Enn bit = 0).
• Period from after reset to start of first DMA transfer
• Period from after channel initialization by DCHCn.INITn bit to start of DMA
transfer
• Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of
the next DMA transfer
p. 617
The DS0 bit specifies the size of the transfer data, and does not control bus
sizing. If 8-bit data (DS0 bit = 0) is set, therefore, the lower data bus is not always
used.
p. 617
If the transfer data size is set to 16 bits (DS0 bit = 1), transfer cannot be started
from an odd address. Transfer is always started from an address with the first bit
of the lower address aligned to 0.
p. 617
Chapter 18
Soft
DMA
function
(DMA
controller)
DADC0 to
DADC3
registers
If DMA transfer is executed on an on-chip peripheral I/O register (as the transfer
source or destination), be sure to specify the same transfer size as the register
size. For example, to execute DMA transfer on an 8-bit register, be sure to specify
8-bit transfer.
p. 617