Datasheet

V850ES/JG3 APPENDIX E LIST OF CAUTIONS
R01UH0015EJ0300 Rev.3.00 Page 856 of 870
Sep 30, 2010
(23/36)
Chapter
Classification
Function Details of
Function
Cautions Page
When
communication
among other
devices are in
progress
When the IICCn.IICEn bit of the V850ES/JG3 is set to 1 while communications
among other devices are in progress, the start condition may be detected
depending on the status of the communication line. Be sure to set the IICCn.IICEn
bit to 1 when the SCL0n and SDA0n lines are high level.
p. 596
Operation
enable
Determine the operation clock frequency by the IICCLn, IICXn, and OCKSm
registers before enabling the operation (IICCn.IICEn bit = 1). To change the
operation clock frequency, clear the IICCn.IICEn bit to 0 once.
p. 596
IICCn.STTn,
SPTn bits
After the IICCn.STTn and IICCn.SPTn bits have been set to 1, they must not be
re-set without being cleared to 0 first.
p. 596
Transmission
reservation
If transmission has been reserved, set the IICCN.SPIEn bit to 1 so that an
interrupt request is generated by the detection of a stop condition. After an
interrupt request has been generated, the wait state will be released by writing
communication data to I
2
Cn, then transferring will begin. If an interrupt is not
generated by the detection of a stop condition, transmission will halt in the wait
state because an interrupt request was not generated. However, it is not
necessary to set the SPIEn bit to 1 for the software to detect the IICSn.MSTSn bit.
p. 596
Master
operation in
single master
system
Release the I
2
C0n bus (SCL0n, SDA0n pins = high level) in conformity with the
specifications of the product in communication.
For example, when the EEPROM outputs a low level to the SDA0n pin, set the
SCL0n pin to the output port and output clock pulses from that output port until
when the SDA0n pin is constantly high level.
p. 598
Confirm that the bus release status (IICCLn.CLDn bit = 1, IICCLn.DADn bit = 1)
has been maintained for a certain period (1 frame, for example). When the SDA0n
pin is constantly low level, determine whether to release the I
2
C0n bus (SCL0n,
SDA0n pins = high level) by referring to the specifications of the product in
communication.
p. 599
Conform the transmission and reception formats to the specifications of the
product in communication.
p. 601
When using the V850ES/JG3 as the master in the multimaster system, read the
IICSn.MSTSn bit for each INTIICn interrupt occurrence to confirm the arbitration
result.
p. 601
Master
operation in
multimaster
system
When using the V850ES/JG3 as the slave in the multimaster system, confirm the
status using the IICSn and IICFn registers for each INTIICn interrupt occurrence
to determine the next processing.
p. 601
pp. Slave wait
cancellation
To cancel slave wait, write FFH to IICn or set WRELn.
606 to 608
pp.
Chapter 17
Soft
I
2
C bus
Master wait
cancellation
To cancel master wait, write FFH to IICn or set WRELn.
609 to 611
Be sure to clear bits 14 to 10 of the DSAnH register to 0. p. 614
Chapter 18
Soft
DMA
function
(DMA
controller)
DSA0 to DSA3
registers
Set the DSAnH and DSAnL registers at the following timing when DMA transfer is
disabled (DCHCn.Enn bit = 0).
• Period from after reset to start of first DMA transfer
• Period from after channel initialization by DCHCn.INITn bit to start of DMA
transfer
• Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of
the next DMA transfer
p. 614