Datasheet

V850ES/JG3 APPENDIX E LIST OF CAUTIONS
R01UH0015EJ0300 Rev.3.00 Page 855 of 870
Sep 30, 2010
(22/36)
Chapter
Classification
Function Details of Function Cautions Page
Set the SPTn bit to 1 only in master mode. However, when the IICRSVn bit is 0,
the SPTn bit must be set to 1 and a stop condition generated before the first
stop condition is detected following the switch to the operation enabled status.
For details, see 17.15 Cautions.
p. 545IICC0 to IICC2
registers
When the TRCn bit = 1, the WRELn bit is set to 1 during the ninth clock and the
wait state is canceled, after which the TRCn bit is cleared to 0 and the SDA0n
line is set to high impedance.
p. 545
Accessing the IICSn register is prohibited in the following statuses. For details,
see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers.
• When the CPU operates with the subclock and the main clock oscillation is
stopped
• When the CPU operates with the internal oscillation clock
p. 546IICS0 to IICS2
registers
The TRCn bit is cleared to 0 and SDA0n line becomes high impedance when
the WRELn bit is set to 1 and the wait state is canceled to 0 at the ninth clock by
TRCn bit = 1.
p. 547
Write the STCENn bit only when operation is stopped (IICEn bit = 0). p. 550
When the STCENn bit = 1, the bus released status (IICBSYn bit = 0) is
recognized regardless of the actual bus status immediately after the I
2
Cn bus
operation is enabled. Therefore, to issue the first start condition (STTn bit = 1), it
is necessary to confirm that the bus has been released, so as to not disturb
other communications.
p. 550
IICF0 to IICF2
registers
Write the IICRSVn bit only when operation is stopped (IICEn bit = 0). p. 550
IICCL0 to IICCL2
registers
Be sure to clear bits 7 and 6 to “0”. p. 551
Since the selection clock is fXX regardless of the value set to the OCKS0
register, clear the OCKS0 register to 00H (I
2
C division clock stopped status).
p. 553
I
2
C0n transfer
clock setting
method
Since the selection clock is f
XX regardless of the value set to the OCKS1
register, clear the OCKS1 register to 00H (I
2
C division clock stopped status).
p. 554
Start condition When the IICCn.IICEn bit of the V850ES/JG3 is set to 1 while communications
with other devices are in progress, the start condition may be detected
depending on the status of the communication line. Be sure to set the
IICCn.IICEn bit to 1 when the SCL0n and SDA0n lines are high level.
p. 558
When the IICCn.WTIMn bit = 1, an INTIICn signal occurs at the falling edge of
the ninth clock. When the WTIMn bit = 0 and the extension code’s slave address
is received, an INTIICn signal occurs at the falling edge of the eighth clock (n =
0 to 2).
p. 590Status during
arbitration and
interrupt request
signal generation
timing
When there is a possibility that arbitration will occur, set the SPIEn bit to 1 for
master device operation (n = 0 to 2).
p. 590
When
IICFn.STCENn bit
= 0
Immediately after the I
2
C0n operation is enabled, the bus communication status
(IICFn.IICBSYn bit = 1) is recognized regardless of the actual bus status. To
execute master communication in the status where a stop condition has not
been detected, generate a stop condition and then release the bus before
starting the master communication.
Use the following sequence for generating a stop condition.
<1> Set the IICCLn register.
<2> Set the IICCn.IICEn bit.
<3> Set the IICCn.SPTn bit.
p. 596
Chapter 17
Soft
I
2
C bus
When
IICFn.STCENn bit
= 1
Immediately after I
2
C0n operation is enabled, the bus released status (IICBSYn
bit = 0) is recognized regardless of the actual bus status. To generate the first
start condition (IICCn.STTn bit = 1), it is necessary to confirm that the bus has
been released, so as to not disturb other communications.
p. 596