Datasheet

V850ES/JG3 APPENDIX E LIST OF CAUTIONS
R01UH0015EJ0300 Rev.3.00 Page 854 of 870
Sep 30, 2010
(21/36)
Chapter
Classification
Function Details of
Function
Cautions Page
Baud rage
generation
Set fBRGm to 8 MHz or lower. p. 531
When
transferring
transmit data
and receive
data using DMA
transfer
When transferring transmit data and receive data using DMA transfer, error
processing cannot be performed even if an overrun error occurs during serial
transfer. Check that the no overrun error has occurred by reading the
CBnSTR.CBnOVE bit after DMA transfer has been completed.
p. 532
CBnCTL0
register
CBnCTL1
register
CBnCTL2
register
In regards to registers that are forbidden from being rewritten during operations
(CBnCTL0.CBnPWR bit is 1), if rewriting has been carried out by mistake during
operations, set the CBnCTL0.CBnPWR bit to 0 once, then initialize CSIBn.
Registers to which rewriting during operation are prohibited are shown below.
• CBnCTL0 register: CBnTXE, CBnRXE, CBnDIR, CBnTMS bits
• CBnCTL1 register: CBnCKP, CBnDAP, CBnCKS2 to CBnCKS0 bits
• CBnCTL2 register: CBnCL3 to CBnCL0 bits
p. 532
Chapter 16
Soft
3-wire
variable-
length
serial I/O
(CSIB)
Communication
types 2, 4
In communication type 2 and 4 (CBnCTL1.CBnDAP bit = 1), the
CBnSTR.CBnTSF bit is cleared half a SCKBn clock after occurrence of a
reception complete interrupt (INTCBnR).
In the single transfer mode, writing the next transmit data is ignored during
communication (CBnTSF bit = 1), and the next communication is not started. Also
if reception-only communication (CBnCTL0.CBnTXE bit = 0, CBnCTL0.CBnRXE
bit = 1) is set, the next communication is not started even if the receive data is
read during communication (CBnTSF bit = 1).
Therefore, when using the single transfer mode with communication type 2 or 4
(CBnDAP bit = 1), pay particular attention to the following.
• To start the next transmission, confirm that CBnTSF bit = 0 and then write the
transmit data to the CBnTX register.
• To perform the next reception continuously when reception-only communication
(CBnTXE bit = 0, CBnRXE bit = 1) is set, confirm that CBnTSF bit = 0 and then
read the CBnRX register.
Or, use the continuous transfer mode instead of the single transfer mode. Use of
the continuous transfer mode is recommend especially for using DMA.
p. 532
I
2
C bus To use the I
2
C bus function, use the P38/SDA00, P39/SCL00, P40/SDA01,
P41/SCL01, P90/SDA02, and P91/SCL02 pins as the serial transmit/receive data
I/O pins (SDA00 to SDA02) and serial clock I/O pins (SCL00 to SCL02),
respectively, and set them to N-ch open-drain output.
p. 533
UARTA2 and
I
2
C00 mode
switching
The transmit/receive operation of UARTA2 and I
2
C00 is not guaranteed if these
functions are switched during transmission or reception. Be sure to disable the
one that is not used.
p. 533
CSIB0 and
I
2
C01 mode
switching
The transmit/receive operation of CSIB0 and I
2
C01 is not guaranteed if these
functions are switched during transmission or reception. Be sure to disable the
one that is not used.
p. 534
UARTA1 and
I
2
C02 mode
switching
The transmit/receive operation of UARTA1 and I
2
C02 is not guaranteed if these
functions are switched during transmission or reception. Be sure to disable the
one that is not used.
p. 535
Chapter 17
Soft
I
2
C bus
IICC0 to IICC2
registers
If the I
2
Cn operation is enabled (IICEn bit = 1) when the SCL0n line is high level
and the SDA0n line is low level, the start condition is detected immediately. To
avoid this, after enabling the I
2
Cn operation, immediately set the LRELn bit to 1
with a bit manipulation instruction.
p. 542