Datasheet

V850ES/JG3 CHAPTER 4 PORT FUNCTIONS
R01UH0015EJ0300 Rev.3.00 Page 71 of 870
Sep 30, 2010
(2) Port 0 mode register (PM0)
1
Output mode
Input mode
PM0n
0
1
I/O mode control (n = 2 to 6)
PM0 PM06 PM05 PM04 PM03 PM02 1 1
After reset: FFH R/W Address: FFFFF420H
(3) Port 0 mode control register (PMC0)
0PMC0 PMC06 PMC05 PMC04 PMC03 PMC02 0 0
I/O port
INTP3 input
PMC06
0
1
Specification of P06 pin operation mode
I/O port
INTP2 input
PMC05
0
1
Specification of P05 pin operation mode
I/O port
INTP1 input
PMC04
0
1
Specification of P04 pin operation mode
I/O port
INTP0 input/ADTRG input
PMC03
0
1
Specification of P03 pin operation mode
I/O port
NMI input
PMC02
0
1
Specification of P02 pin operation mode
After reset: 00H R/W Address: FFFFF440H
Caution The P05/INTP2/DRST pin becomes the DRST pin regardless of the value of the PMC05
bit when the OCDM.OCDM0 bit = 1.