Datasheet

V850ES/JG3 APPENDIX E LIST OF CAUTIONS
R01UH0015EJ0300 Rev.3.00 Page 853 of 870
Sep 30, 2010
(20/36)
Chapter
Classification
Function Details of
Function
Cautions Page
Start up
UARTAn
Start up the UARTAn in the following sequence.
<1> Set the UAnCTL0.UAnPWR bit to 1.
<2> Set the ports.
<3> Set the UAnCTL0.UAnTXE bit to 1, UAnCTL0.UAnRXE bit to 1.
p. 483
Stop UARTAn Stop the UARTAn in the following sequence.
<1> Set the UAnCTL0.UAnTXE bit to 0, UAnCTL0.UAnRXE bit to 0.
<2> Set the ports and set the UAnCTL0.UAnPWR bit to 0 (it is not a problem if
port setting is not changed).
p. 483
Transmit mode In transmit mode (UAnCTL0.UAnPWR bit = 1 and UAnCTL0.UAnTXE bit = 1), do
not overwrite the same value to the UAnTX register by software because
transmission starts by writing to this register. To transmit the same value
continuously, overwrite the same value.
p. 483
Chapter 15
Soft
Asynchro-
nous serial
interface A
(UARTA)
Continuous
transmission
In continuous transmission, the communication rate from the stop bit to the next
start bit is extended 2 base clocks more than usual. However, the reception side
initializes the timing by detecting the start bit, so the reception result is not
affected.
p. 483
CSIB4 and
UARTA0 mode
switching
The transmit/receive operation of CSIB4 and UARTA0 is not guaranteed if these
functions are switched during transmission or reception. Be sure to disable the
one that is not used.
p. 484
CSIB0 and
I
2
C01 mode
switching
The transmit/receive operation of CSIB0 and I
2
C01 is not guaranteed if these
functions are switched during transmission or reception. Be sure to disable the
one that is not used.
p. 485
To forcibly suspend transmission/reception, clear the CBnPWR bit to 0 instead of
the CBnRXE and CBnTXE bits. At this time, the clock output is stopped.
p. 488CBnCTL0
register
Be sure to clear bits 3 and 2 to “0”. p. 490
The CBnCTL1 register can be rewritten only when the CBnCTL0.CBnPWR bit =
0.
p. 491CBnCTL1
register
Set the communication clock (f
CCLK) to 8 MHz or lower. p. 491
CBnCTL2
register
The CBnCTL2 register can be rewritten only when the CBnCTL0.CBnPWR bit = 0
or when both the CBnTXE and CBnRXE bits = 0.
p. 492
Continuous
transfer mode
(master mode,
transmission
mode)
In continuous transmission mode, the reception completion interrupt request
signal (INTCBnR) is not generated.
p. 509
Continuous
transfer mode
(slave mode,
transmission
mode)
In continuous transmission mode, the reception completion interrupt request
signal (INTCBnR) is not generated.
p. 518
Clock timing In single transfer mode, writing to the CBnTX register with the CBnTSF bit set to 1
is ignored. This has no influence on the operation during transfer.
For example, if the next data is written to the CBnTX register when DMA is started
by generating the INTCBnR signal, the written data is not transferred because the
CBnTSF bit is set to 1.
Use the continuous transfer mode, not the single transfer mode, for such
applications.
p. 527
Do not rewrite the PRSMm register during operation. p. 530
PRSM1 to
PRSM3 registers
Set the PRSMm register before setting the BGCEm bit to 1. p. 530
Do not rewrite the PRSCMm register during operation. p. 531
Chapter 16
Soft
3-wire
variable-
length
serial I/O
(CSIB)
PRSCM1 to
PRSCM3
registers
Set the PRSCMm register before setting the PRSMm.BGCEm bit to 1. p. 531