Datasheet

V850ES/JG3 APPENDIX E LIST OF CAUTIONS
R01UH0015EJ0300 Rev.3.00 Page 852 of 870
Sep 30, 2010
(19/36)
Chapter
Classification
Function Details of
Function
Cautions Page
The operation during reception is performed assuming that there is only one stop
bit. A second stop bit is ignored.
p. 470
When reception is completed, read the UAnRX register after the reception
complete interrupt request signal (INTUAnR) has been generated, and clear the
UAnPWR or UAnRXE bit to 0. If the UAnPWR or UAnRXE bit is cleared to 0
before the INTUAnR signal is generated, the read value of the UAnRX register
cannot be guaranteed.
p. 470
UART
reception
If receive completion processing (INTUAnR signal generation) of UARTAn and
the UAnPWR bit = 0 or UAnRXE bit = 0 conflict, the INTUAnR signal may be
generated in spite of these being no data stored in the UAnRX register.
To complete reception without waiting INTUAnR signal generation, be sure to
clear (0) the interrupt request flag (UAnRIF) of the UAnRIC register, after setting
(1) the interrupt mask flag (UAnRMK) of the interrupt control register (UAnRIC)
and then set (1) the UAnPWR bit = 0 or UAnRXE bit = 0.
p. 470
When an INTUAnR signal is generated, the UAnSTR register must be read to
check for errors.
p. 471Reception
errors
If a receive error interrupt occurs during continuous reception, read the contents
of the UAnSTR register must be read before the next reception is completed, then
perform error processing.
p. 472
LIN function When using the LIN function, fix the UAnPS1 and UAnPS0 bits of the UAnCTL0
register to 00.
p. 473
UAnCTL1
register
Clear the UAnCTL0.UAnPWR bit to 0 before rewriting the UAnCTL1 register. p. 476
UAnCTL2
register
Clear the UAnCTL0.UAnPWR bit to 0 or clear the UAnTXE and UAnRXE bits to
00 before rewriting the UAnCTL2 register.
p. 477
The baud rate error during transmission must be within the error tolerance on the
receiving side.
p. 478Baud rate error
The baud rate error during reception must satisfy the range indicated in (5)
Allowable baud rate range during reception.
p. 478
Allowable baud
rate range
during
reception
The baud rate error during reception must be set within the allowable error range
using the following equation.
p. 480
When the clock
supply to
UARTAn is
stopped
When the clock supply to UARTAn is stopped (for example, in IDLE1, IDLE2, or
STOP mode), the operation stops with each register retaining the value it had
immediately before the clock supply was stopped. The TXDAn pin output also
holds and outputs the value it had immediately before the clock supply was
stopped. However, the operation is not guaranteed after the clock supply is
resumed. Therefore, after the clock supply is resumed, the circuits should be
initialized by setting the UAnCTL0.UAnPWR, UAnCTL0.UAnRXEn, and
UAnCTL0.UAnTXEn bits to 000.
p. 483
RXDA1 pin
KR7 pin
The RXDA1 and KR7 pins must not be used at the same time. To use the RXDA1
pin, do not use the KR7 pin. To use the KR7 pin, do not use the RXDA1 pin (it is
recommended to set the PFC91 bit to 1 and clear PFCE91 bit to 0).
p. 483
Chapter 15
Soft
Asynchro-
nous serial
interface A
(UARTA)
Performing the
transfer of
transmit data
and receive
data using
DMA transfer
In UARTAn, the interrupt caused by a communication error does not occur. When
performing the transfer of transmit data and receive data using DMA transfer,
error processing cannot be performed even if errors (parity, overrun, framing)
occur during transfer. Either read the UAnSTR register after DMA transfer has
been completed to make sure that there are no errors, or read the UAnSTR
register during communication to check for errors.
p. 483