Datasheet

V850ES/JG3 APPENDIX E LIST OF CAUTIONS
R01UH0015EJ0300 Rev.3.00 Page 851 of 870
Sep 30, 2010
(18/36)
Chapter
Classification
Function Details of
Function
Cautions Page
DAC0 and DAC1 share the AVREF1 pin. p. 442D/A converter
DAC0 and DAC1 share the AV
SS pin. The AVSS pin is also shared by the A/D
converter.
p. 442
Hard
DA0M register The output trigger in the real-time output mode (DA0MDn bit = 1) is as follows.
• When n = 0: INTTP2CC0 signal (see CHAPTER 7 16-BIT TIMER/EVENT
COUNTER P (TMP))
• When n = 1: INTTP3CC0 signal (see CHAPTER 7 16-BIT TIMER/EVENT
COUNTER P (TMP))
p. 443
DA0CS0,
DA0CS1
registers
In the real-time output mode (DA0M.DA0MDn bit = 1), set the DA0CSn register
before the INTTP2CC0/INTTP3CC0 signals are generated. D/A conversion starts
when the INTTP2CC0/INTTP3CC0 signals are generated.
p. 444
Do not change the set value of the DA0CSn register while the trigger signal is
being issued in the real-time output mode.
p. 446
Before changing the operation mode, be sure to clear the DA0M.DA0CEn bit to 0. p. 446
Soft
When using one of the P10/AN00 and P11/AN01 pins as an I/O port and the other
as a D/A output pin, do so in an application where the port I/O level does not
change during D/A output.
p. 446
Make sure that AVREF0 = VDD = AVREF1 = 3.0 to 3.6 V. If this range is exceeded, the
operation is not guaranteed.
p. 446
Apply power to AVREF1 at the same timing as AVREF0. p. 446
Hard
No current can be output from the ANOn pin (n = 0, 1) because the output
impedance of the D/A converter is high. When connecting a resistor of 2 MΩ or
less, insert a JFET input operational amplifier between the resistor and the ANOn
pin.
p. 446
Chapter 14
Soft
D/A
converter
Cautions
Because the D/A converter stops operation in the STOP mode, the ANO0 and
ANO1 pins go into a highimpedance state, and the power consumption can be
reduced.
In the IDLE1, IDLE2, or subclock operation mode, however, the operation
continues. To lower the power consumption, therefore, clear the DA0M.DA0CEn
bit to 0.
p. 446
CSIB4 and
UARTA0 mode
switching
The transmit/receive operation of CSIB4 and UARTA0 is not guaranteed if these
functions are switched during transmission or reception. Be sure to disable the
one that is not used.
p. 447
UARTA2 and
I
2
C00 mode
switching
The transmit/receive operation of UARTA2 and I
2
C00 is not guaranteed if these
functions are switched during transmission or reception. Be sure to disable the
one that is not used.
p. 448
UARTA1 and
I
2
C02 mode
switching
The transmit/receive operation of UARTA1 and I
2
C02 is not guaranteed if these
functions are switched during transmission or reception. Be sure to disable the
one that is not used.
p. 449
UAnOPT0
register
Do not set the UAnSRT and UAnSTT bits (to 1) during SBF reception (UAnSRF
bit = 1).
p. 455
If SBF is transmitted during a data reception, a framing error occurs. p. 465SBF reception
Do not set the SBF reception trigger bit (UAnSRT) and SBF transmission trigger
bit (UAnSTT) to 1 during an SBF reception (UAnSRF = 1).
p. 465
Continuous
transmission
When initializing transmissions during the execution of continuous transmissions,
make sure that the UAnSTR.UAnTSF bit is 0, then perform the initialization.
Transmit data that is initialized when the UAnTSF bit is 1 cannot be guaranteed.
p. 466
Chapter 15
Soft
Asynchro-
nous serial
interface A
(UARTA)
UART
reception
Be sure to read the UAnRX register even when a reception error occurs. If the
UAnRX register is not read, an overrun error occurs during reception of the next
data, and reception errors continue occurring indefinitely.
p. 470