Datasheet

V850ES/JG3 APPENDIX E LIST OF CAUTIONS
R01UH0015EJ0300 Rev.3.00 Page 846 of 870
Sep 30, 2010
(13/36)
Chapter
Classification
Function Details of
Function
Cautions Page
If the WDTM2 register is rewritten twice after reset, an overflow signal is forcibly
generated and the counter is reset.
p. 396
To intentionally generate an overflow signal, write data to the WDTM2 register
only twice, or write a value other than “ACH” to the WDTE register only once.
However, when watchdog timer 2 is set to stop operation, an overflow signal is
not generated even if data is written to the WDTM2 register only twice, or a value
other than “ACH” is written to the WDTE register only once.
p. 396
WDTM2 register
To stop the operation of watchdog timer 2, set the RCM.RSTOP bit to 1 (to stop
the internal oscillator) and write 00H in the WDTM2 register. If the RCM.RSTOP
bit cannot be set to 1, set the WDCS23 bit to 1 (2
n
/fXX is selected and the clock
can be stopped in the IDLE1, IDLW2, sub-IDLE, and subclock operation modes).
p. 396
When a value other than “ACH” is written to the WDTE register, an overflow
signal is forcibly output.
p. 397
When a 1-bit memory manipulation instruction is executed for the WDTE register,
an overflow signal is forcibly output.
p. 397
To intentionally generate an overflow signal, write a value other than “ACH” to the
WDTE register only once, or write data to the WDTM2 register only twice.
However, when the watchdog timer 2 is set to stop operation, an overflow signal
is not generated even if data is written to the WDTM2 register only twice, or a
value other than “ACH” is written to the WDTE register only once.
p. 397
Chapter 11
Soft
Watchdog
timer 2
function
WDTE register
The read value of the WDTE register is “9AH” (which differs from written value
“ACH”).
p. 397
When writing to bits 6 and 7 of the RTBH0 register, always write 0. p. 401
Accessing the RTBL0 and RTBH0 registers is prohibited in the following statuses.
For details, see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers.
• When the CPU operates with the subclock and the main clock oscillation is
stopped
• When the CPU operates with the internal oscillation clock
p. 401
RTBL0, RTBH0
registers
After setting the real-time output port, set output data to the RTBL0 and RTBH0
registers by the time a realtime output trigger is generated.
p. 401
By enabling the real-time output operation (RTPC0.RTPOE0 bit = 1), the bits
enabled to real-time output among the RTP00 to RTP05 signals perform realtime
output, and the bits set to port mode output 0.
p. 402
If real-time output is disabled (RTPOE0 bit = 0), the real-time output pins (RTP00
to RTP05) all output 0, regardless of the RTPM0 register setting.
p. 402
RTPM0 register
In order to use this register as the real-time output pins (RTP00 to RTP05), set
these pins as real-time output port pins using the PMC and PFC registers.
p. 402
RTPC0 register Set the RTPEG0, BYTE0, and EXTR0 bits only when RTPOE0 bit = 0. p. 403
Real-time
output operation
Prevent the following conflicts by software.
• Conflict between real-time output disable/enable switching (RTPOE0 bit) and
selected real-time output trigger.
• Conflict between writing to the RTBH0 and RTBL0 registers in the real-time
output enabled status and the selected real-time output trigger.
p. 405
Initialization Before performing initialization, disable real-time output (RTPOE0 bit = 0). p. 405
Chapter 12
Soft
Real-time
output
function
(RTO)
RTBH0, RTBL0
registers
Once real-time output has been disabled (RTPOE0 bit = 0), be sure to initialize
the RTBH0 and RTBL0 registers before enabling real-time output again (RTPOE0
bit = 0 → 1).
p. 405