Datasheet

V850ES/JG3 APPENDIX E LIST OF CAUTIONS
R01UH0015EJ0300 Rev.3.00 Page 845 of 870
Sep 30, 2010
(12/36)
Chapter
Classification
Function Details of
Function
Cautions Page
Set the TM0CKS2 to TM0CKS0 bits when TM0CE bit = 0.
When changing the value of TM0CE from 0 to 1, it is not possible to set the value
of the TM0CKS2 to TM0CKS0 bits simultaneously.
p. 378
TM0CTL0
register
Be sure to clear bits 3 to 6 to “0”.
p. 378
pp.
Operation in
interval timer
mode
Do not set the TM0CMP0 register to FFFFH.
379, 382
Count start It takes the 16-bit counter up to the following time to start counting after the
TM0CTL0.TM0CE bit is set to 1, depending on the count clock selected.
p. 383
Chapter 9
Soft
16-bit
interval
timer M
(TMM)
TM0CMP0,
TM0CTL0
registers
Rewriting the TM0CMP0 and TM0CTL0 registers is prohibited while TMM0 is
operating.
If these registers are rewritten while the TM0CE bit is 1, the operation cannot be
guaranteed.
If they are rewritten by mistake, clear the TM0CTL0.TM0CE bit to 0, and re-set
the registers.
p. 383
Do not change the values of the BGCS00 and BGCS01 bits during watch timer
operation.
p. 387
Set the PRSM0 register before setting the BGCE0 bit to 1. p. 387
PRSM0 register
Set the PRSM0 and PRSCM0 registers according to the main clock frequency
that is used so as to obtain an f
BRG frequency of 32.768 kHz.
p. 387
Do not rewrite the PRSCM0 register during watch timer operation. p. 388
Set the PRSCM0 register before setting the PRSM0.BGCE0 bit to 1. p. 388
PRSCM0
register
Set the PRSM0 and PRSCM0 registers according to the main clock frequency
that is used so as to obtain an f
BRG frequency of 32.768 kHz.
p. 388
WTM register Rewrite the WTM2 to WTM7 bits while both the WTM0 and WTM1 bits are 0. p. 390
Soft
Some time is required before the first watch timer interrupt request signal
(INTWT) is generated after operation is enabled (WTM.WTM1 and WTM.WTM0
bits = 1).
p. 393
Chapter 10
Hard
Watch
timer
functions
Cautions
It takes 0.515625 seconds (max.) for the first INTWT signal to be generated (2
9
×
1/32768 = 0.015625 seconds longer (max.)).
The INTWT signal is then generated every 0.5 seconds.
p. 393
Watchdog timer 2 automatically starts in the reset mode following reset release.
When watchdog timer 2 is not used, either stop its operation before reset is
executed via this function, or clear watchdog timer 2 once and stop it within the
next interval time.
Also, write to the WDTM2 register for verification purposes only once, even if the
default settings (reset mode, interval time: f
R/2
19
) do not need to be changed.
p. 394
Default-start
watchdog timer
For the non-maskable interrupt servicing due to a non-maskable interrupt request
signal (INTWDT2), see 19.2.2 (2) From INTWDT2 signal.
p. 394
Accessing the WDTM2 register is prohibited in the following statuses. For details,
see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers.
• When the CPU operates with the subclock and the main clock oscillation is
stopped
• When the CPU operates with the internal oscillation clock
p. 396
For details of the WDCS20 to WDCS24 bits, see Table 11-2 Watchdog Timer 2
Clock Selection.
p. 396
Chapter 11
Soft
Watchdog
timer 2
function
WDTM2 register
Although watchdog timer 2 can be stopped just by stopping the operation of the
internal oscillator, clear the WDTM2 register to 00H to securely stop the timer (to
avoid selection of the main clock or subclock due to an erroneous write
operation).
p. 396