Datasheet

V850ES/JG3 APPENDIX E LIST OF CAUTIONS
R01UH0015EJ0300 Rev.3.00 Page 843 of 870
Sep 30, 2010
(10/36)
Chapter
Classification
Function Details of
Function
Cautions Page
Rewrite the TQ0IS7 to TQ0IS0 bits when the TQ0CTL0.TQ0CE bit = 0. (The
same value can be written when the TQ0CE bit = 1.) If rewriting was mistakenly
performed, clear the TQ0CE bit to 0 and then set the bits again.
p. 284TQ0IOC1
register
The TQ0IS7 to TQ0IS0 bits are valid only in the freerunning timer mode and the
pulse width measurement mode. In all other modes, a capture operation is not
possible.
p. 284
Rewrite the TQ0EES1, TQ0EES0, TQ0ETS1, and TQ0ETS0 bits when the
TQ0CTL0.TQ0CE bit = 0. (The same value can be written when the TQ0CE bit =
1.) If rewriting was mistakenly performed, clear the TQ0CE bit to 0 and then set
the bits again.
p. 285
The TQ0EES1 and TQ0EES0 bits are valid only when the TQ0CTL1.TQ0EEE bit
= 1 or when the external event count mode (TQ0CTL1.TQ0MD2 to
TQ0CTL1.TQ0MD0 bits = 001) has been set.
p. 285
TQ0IOC2
register
The TQ0ETS1 and TQ0ETS0 bits are valid only when the external trigger pulse
output mode (TQ0CTL1.TQ0MD2 to TQ0CTL1.TQ0MD0 bits = 010) or the one-
shot pulse output mode (TQ0CTL1.TQ0MD2 to TQ0CTL1.TQ0MD0 = 011) is set.
p. 285
Rewrite the TQ0CCS3 to TQ0CCS0 bits when the TQ0CTL0.TQ0CE bit = 0. (The
same value can be written when the TQ0CE bit = 1.) If rewriting was mistakenly
performed, clear the TQ0CE bit to 0 and then set the bits again.
p. 286TQ0OPT0
register
Be sure to clear bits 1 to 3 to “0”. p. 286
TQ0CCR0
register
Accessing the TQ0CCR0 register is prohibited in the following statuses. For
details, see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers.
• When the CPU operates with the subclock and the main clock oscillation is
stopped
• When the CPU operates with the internal oscillation clock
p. 287
TQ0CCR1
register
Accessing the TQ0CCR1 register is prohibited in the following statuses. For
details, see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers.
• When the CPU operates with the subclock and the main clock oscillation is
stopped
• When the CPU operates with the internal oscillation clock
p. 289
TQ0CCR2
register
Accessing the TQ0CCR2 register is prohibited in the following statuses. For
details, see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers.
• When the CPU operates with the subclock and the main clock oscillation is
stopped
• When the CPU operates with the internal oscillation clock
p. 291
TQ0CCR3
register
Accessing the TQ0CCR3 register is prohibited in the following statuses. For
details, see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers.
• When the CPU operates with the subclock and the main clock oscillation is
stopped
• When the CPU operates with the internal oscillation clock
p. 293
TQ0CNT
register
Accessing the TQ0CNT register is prohibited in the following statuses. For details,
see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers.
• When the CPU operates with the subclock and the main clock oscillation is
stopped
• When the CPU operates with the internal oscillation clock
p. 295
Chapter 8
Soft
16-bit
timer/
event
counter Q
(TMQ)
External event
count mode
To use the external event count mode, specify that the valid edge of the TIQ00
pin capture trigger input is not detected (by clearing the TQ0IOC1.TQ0IS1 and
TQ0IOC1.TQ0IS0 bits to “00”).
p. 296