Datasheet

V850ES/JG3 APPENDIX E LIST OF CAUTIONS
R01UH0015EJ0300 Rev.3.00 Page 842 of 870
Sep 30, 2010
(9/36)
Chapter
Classification
Function Details of
Function
Cautions Page
TPnIOC0,
TPnOE0,
TPnOL0 bits
Clear this bit to 0 when the TOPn0 pin is not used in the external trigger pulse
output mode.
p. 224
Note on
changing pulse
width during
operation
To change the PWM waveform while the counter is operating, write the TPnCCR1
register last.
Rewrite the TPnCCRm register after writing the TPnCCR1 register after the
INTTPnCC0 signal is detected.
p. 228
TPnIOC0.TPnOE0,
TPnOL0 bits
Clear this bit to 0 when the TOPn0 pin is not used in the one-shot pulse output
mode.
p. 236
Register setting
for operation in
one-shot pulse
output mode
One-shot pulses are not output even in the one-shot pulse output mode, if the
value set in the TPnCCR1 register is greater than that set in the TPnCCR0
register.
p. 237
Note on
rewriting
TPnCCRm
register
To change the set value of the TPnCCRm register to a smaller value, stop
counting once, and then change the set value.
If the value of the TPnCCRm register is rewritten to a smaller value during
counting, the 16-bit counter may overflow.
p. 239
TPnIOC0.TPnOE0,
TPnOL0 bits
Clear this bit to 0 when the TOPn0 pin is not used in the PWM output mode. p. 243
When using the selector function, be sure to set the port/timer alternate function
pins for TMP to be connected to the capture trigger input.
p. 274Selector function
Disable the peripheral I/Os to be connected (TMP/UARTA) before setting the
selector function.
p. 274
When setting the ISEL3 or ISEL4 bit to “1”, be sure to set the corresponding
alternate-function pin to the capture trigger input.
p. 275SELCNT0
register
Be sure to clear bits 7 to 5, and 2 to 0 to “0”. p. 275
Chapter 7
Soft
16-bit
timer/
event
counter P
(TMP)
Capture
operation
When the capture operation is used and a slow clock is selected as the count
clock, FFFFH, not 0000H, may be captured in the TPnCCR0 and TPnCCR1
registers if the capture trigger is input immediately after the TPnCE bit is set to 1.
p. 276
Set the TQ0CKS2 to TQ0CKS0 bits when the TQ0CE bit = 0. When the value of
the TQ0CE bit is changed from 0 to 1, the TQ0CKS2 to TQ0CKS0 bits can be set
simultaneously.
p. 281TQ0CTL0
register
Be sure to clear bits 3 to 6 to “0”. p. 281
The TQ0EST bit is valid only in the external trigger pulse output mode or one-shot
pulse output mode. In any other mode, writing 1 to this bit is ignored.
p. 282
External event count input is selected in the external event count mode regardless
of the value of the TQ0EEE bit.
p. 282
Set the TQ0EEE and TQ0MD2 to TQ0MD0 bits when the TQ0CTL0.TQ0CE bit =
0. (The same value can be written when the TQ0CE bit = 1.) The operation is not
guaranteed when rewriting is performed with the TQ0CE bit = 1. If rewriting was
mistakenly performed, clear the TQ0CE bit to 0 and then set the bits again.
p. 282
TQ0CTL1
register
Be sure to clear bits 3, 4, and 7 to “0”. p. 282
Rewrite the TQ0OLm and TQ0OEm bits when the TQ0CTL0.TQ0CE bit = 0. (The
same value can be written when the TQ0CE bit = 1.) If rewriting was mistakenly
performed, clear the TQ0CE bit to 0 and then set the bits again.
p. 283
Chapter 8
Soft
16-bit
timer/
event
counter Q
(TMQ)
TQ0IOC0
register
Even if the TQ0OLm bit is manipulated when the TQ0CE and TQ0OEm bits are 0,
the TOQ0m pin output level varies.
p. 283