Datasheet

V850ES/JG3 APPENDIX E LIST OF CAUTIONS
R01UH0015EJ0300 Rev.3.00 Page 841 of 870
Sep 30, 2010
(8/36)
Chapter
Classification
Function Details of
Function
Cautions Page
TPnIOC2
register
The TPnETS1 and TPnETS0 bits are valid only when the external trigger pulse
output mode (TPnCTL1.TPnMD2 to TPnCTL1.TPnMD0 bits = 010) or the one-
shot pulse output mode (TPnCTL1.TPnMD2 to TPnCTL1.TPnMD0 = 011) is set.
p. 196
Rewrite the TPnCCS1 and TPnCCS0 bits when the TPnCE bit = 0. (The same
value can be written when the TPnCE bit = 1.) If rewriting was mistakenly
performed, clear the TPnCE bit to 0 and then set the bits again.
p. 197TPnOPT0
register
Be sure to clear bits 1 to 3, 6, and 7 to “0”. p. 197
TPnCCR0
register
Accessing the TPnCCR0 register is prohibited in the following statuses. For
details, see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers.
• When the CPU operates with the subclock and the main clock oscillation is
stopped
• When the CPU operates with the internal oscillation clock
p. 198
TPnCCR1
register
Accessing the TPnCCR1 register is prohibited in the following statuses. For
details, see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers.
• When the CPU operates with the subclock and the main clock oscillation is
stopped
• When the CPU operates with the internal oscillation clock
p. 200
TPnCNT
register
Accessing the TPnCNT register is prohibited in the following statuses. For details,
see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers.
• When the CPU operates with the subclock and the main clock oscillation is
stopped
• When the CPU operates with the internal oscillation clock
p. 202
To use the external event count mode, specify that the valid edge of the TIPn0 pin
capture trigger input is not detected (by clearing the TPnIOC1.TPnIS1 and
TPnIOC1.TPnIS0 bits to “00”).
p. 203Operation
When using the external trigger pulse output mode, one-shot pulse output mode,
and pulse width measurement mode, select the internal clock as the count clock
(by clearing the TPnCTL1.TPnEEE bit to 0).
p. 203
Interval timer
mode (TPnMD2
to TPnMD0 bits
= 000)
This bit can be set to 1 only when the interrupt request signals (INTTPnCC0 and
INTTPnCC1) are masked by the interrupt mask flags (TPnCCMK0 and
TPnCCMK1) and timer output (TOPn1) is performed at the same time. However,
set the TPnCCR0 and TPnCCR1 registers to the same value (see 7.5.1 (2) (d)
Operation of TPnCCR1 register).
p. 205
Notes on
rewriting
TPnCCR0
register
To change the value of the TPnCCR0 register to a smaller value, stop counting
once and then change the set value.
If the value of the TPnCCR0 register is rewritten to a smaller value during
counting, the 16-bit counter may overflow.
p. 210
Register setting
for operation in
external event
count mode
When an external clock is used as the count clock, the external clock can be input
only from the TIPn0 pin. At this time, set the TPnIOC1.TPnIS1 and
TPnIOC1.TPnIS0 bits to 00 (capture trigger input (TIPn0 pin): no edge detection).
p. 216
In the external event count mode, do not set the TPnCCR0 register to 0000H. p. 218External event
count mode
(TPnMD2 to
TPnMD0 bits =
001)
In the external event count mode, use of the timer output is disabled. If performing
timer output using external event count input, set the interval timer mode, and
select the operation enabled by the external event count input for the count clock
(TPnCTL1.TPnMD2 to TPnCTL1.TPnMD0 bits = 000, TPnCTL1.TPnEEE bit = 1).
p. 218
Chapter 7
Soft
16-bit
timer/
event
counter P
(TMP)
Notes on
rewriting the
TPnCCR0
register
To change the value of the TPnCCR0 register to a smaller value, stop counting
once and then change the set value.
If the value of the TPnCCR0 register is rewritten to a smaller value during
counting, the 16-bit counter may overflow.
p. 219