Datasheet

V850ES/JG3 APPENDIX E LIST OF CAUTIONS
R01UH0015EJ0300 Rev.3.00 Page 840 of 870
Sep 30, 2010
(7/36)
Chapter
Classification
Function Details of
Function
Cautions Page
The internal oscillator cannot be stopped while the CPU is operating on the
internal oscillation clock (CCLS.CCLSF bit = 1). Do not set the RSTOP bit to 1.
p. 182
RCM register
The internal oscillator oscillates if the CCLS.CCLSF bit is set to 1 (when WDT
overflow occurs during oscillation stabilization) even when the RSTOP bit is set to
1. At this time, the RSTOP bit remains being set to 1.
p. 182
When the PLLON bit is cleared to 0, the SELPLL bit is automatically cleared to 0
(clockthrough mode).
p. 184
PLLCTL
register
The SELPLL bit can be set to 1 only when the PLL clock frequency is stabilized. If
not (unlocked), “0” is written to the SELPLL bit if data is written to it.
p. 184
The PLL mode cannot be used at fX = 5.0 to 10.0 MHz. p. 185
Before changing the multiplication factor between 4 and 8 by using the CKC
register, set the clock-through mode and stop the PLL.
p. 185
CKC register
Be sure to set bits 3 and 1 to “1” and clear bits 7 to 4 and 2 to “0”. p. 185
LOCKR register The LOCK register does not reflect the lock status of the PLL in real time. p. 186
Set so that the lockup time is 800 μ s or longer. p. 187
Chapter 6
Soft
Clock
generation
function
PLLS register
Do not change the PLLS register setting during the lockup period. p. 187
Set the TPnCKS2 to TPnCKS0 bits when the TPnCE bit = 0. When the value of
the TPnCE bit is changed from 0 to 1, the TPnCKS2 to TPnCKS0 bits can be set
simultaneously.
p. 192TPnCTL0
register
Be sure to clear bits 3 to 6 to “0”. p. 192
The TPnEST bit is valid only in the external trigger pulse output mode or one-shot
pulse output mode. In any other mode, writing 1 to this bit is ignored.
p. 193
External event count input is selected in the external event count mode regardless
of the value of the TPnEEE bit.
p. 193
Set the TPnEEE and TPnMD2 to TPnMD0 bits when the TPnCTL0.TPnCE bit =
0. (The same value can be written when the TPnCE bit = 1.) The operation is not
guaranteed when rewriting is performed with the TPnCE bit = 1. If rewriting was
mistakenly performed, clear the TPnCE bit to 0 and then set the bits again.
p. 193
TPnCTL1
register
Be sure to clear bits 3, 4, and 7 to “0”. p. 193
Rewrite the TPnOL1, TPnOE1, TPnOL0, and TPnOE0 bits when the
TPnCTL0.TPnCE bit = 0. (The same value can be written when the TPnCE bit =
1.) If rewriting was mistakenly performed, clear the TPnCE bit to 0 and then set
the bits again.
p. 194TPnIOC0
register
Even if the TPnOLm bit is manipulated when the TPnCE and TPnOEm bits are 0,
the TOPnm pin output level varies (m = 0, 1).
p. 194
Rewrite the TPnIS3 to TPnIS0 bits when the TPnCTL0.TPnCE bit = 0. (The same
value can be written when the TPnCE bit = 1.) If rewriting was mistakenly
performed, clear the TPnCE bit to 0 and then set the bits again.
p. 195TPnIOC1
register
The TPnIS3 to TPnIS0 bits are valid only in the freerunning timer mode and the
pulse width measurement mode. In all other modes, a capture operation is not
possible.
p. 195
Rewrite the TPnEES1, TPnEES0, TPnETS1, and TPnETS0 bits when the
TPnCTL0.TPnCE bit = 0. (The same value can be written when the TPnCE bit =
1.) If rewriting was mistakenly performed, clear the TPnCE bit to 0 and then set
the bits again.
p. 196
Chapter 7
Soft
16-bit
timer/
event
counter P
(TMP)
TPnIOC2
register
The TPnEES1 and TPnEES0 bits are valid only when the TPnCTL1.TPnEEE bit =
1 or when the external event count mode (TPnCTL1.TPnMD2 to
TPnCTL1.TPnMD0 bits = 001) has been set.
p. 196