Datasheet

V850ES/JG3 APPENDIX E LIST OF CAUTIONS
R01UH0015EJ0300 Rev.3.00 Page 839 of 870
Sep 30, 2010
(6/36)
Chapter
Classification
Function Details of
Function
Cautions Page
Pin status when
internal ROM
When a write access is performed to the internal ROM area, address, data, and
control signals are activated in the same way as access to the external memory
area.
p. 150
EXIMC register Set the EXIMC register from the internal ROM or internal RAM area before
making an external access.
After setting the EXIMC register, be sure to insert a NOP instruction.
p. 152
Write to the BSC register after reset, and then do not change the set values. Also,
do not access an external memory area until the initial settings of the BSC
register are complete.
p. 153BSC register
Be sure to set bits 14, 12, 10, and 8 to “1”, and clear bits 15, 13, 11, 9, 7, 5, 3,
and 1 to “0”.
p. 153
The internal ROM and internal RAM areas are not subject to programmable wait,
and are always accessed without a wait state. The on-chip peripheral I/O area is
also not subject to programmable wait, and only wait control from each peripheral
function is performed.
p. 161
Write to the DWC0 register after reset, and then do not change the set values.
Also, do not access an external memory area until the initial settings of the DWC0
register are complete.
p. 161
When the V850ES/JG3 is used in separate bus mode and operated at fXX > 20
MHz, be sure to insert one or more waits.
p. 161
DWC0 register
Be sure to clear bits 15, 11, 7, and 3 to “0”. p. 161
Address setup wait and address hold wait cycles are not inserted when the
internal ROM area, internal RAM area, and on-chip peripheral I/O areas are
accessed.
p. 164
Write to the AWC register after reset, and then do not change the set values.
Also, do not access an external memory area until the initial settings of the AWC
register are complete.
p. 164
When the V850ES/JG3 is operated at fXX > 20 MHz, be sure to insert the address
hold wait and the address setup wait.
p. 164
AWC register
Be sure to set bits 15 to 8 to “1”. p. 164
The internal ROM, internal RAM, and on-chip peripheral I/O areas are not subject
to idle state insertion.
p. 165
Write to the BCC register after reset, and then do not change the set values. Also,
do not access an external memory area until the initial settings of the BCC
register are complete.
p. 165
Chapter 5
Soft
Bus
control
functions
BCC register
Be sure to set bits 15, 13, 11, and 9 to “1”, and clear bits 14, 12, 10, 8, 6, 4, 2,
and 0 to “0”.
p. 165
Do not change the CPU clock (by using the CK3 to CK0 bits) while CLKOUT is
being output.
p. 179
Use a bit manipulation instruction to manipulate the CK3 bit. When using an 8-bit
manipulation instruction, do not change the set values of the CK2 to CK0 bits.
p. 179
When stopping the main clock, stop the PLL. Also stop the operations of the on-
chip peripheral functions operating with the main clock.
p. 180
If the following conditions are not satisfied, change the CK2 to CK0 bits so that
the conditions are satisfied, then change to the subclock operation mode.
Internal system clock (f
CLK) > Subclock (fXT: 32.768 kHz) × 4
p. 180
Chapter 6
Soft
Clock
generation
function
PCC register
Enable operation of the on-chip peripheral functions operating with the main clock
only after the oscillation of the main clock stabilizes. If their operations are
enabled before the lapse of the oscillation stabilization time, a malfunction may
occur.
p. 181