Datasheet

V850ES/JG3 APPENDIX E LIST OF CAUTIONS
R01UH0015EJ0300 Rev.3.00 Page 835 of 870
Sep 30, 2010
(2/36)
Chapter
Classification
Function Details of
Function
Cautions Page
Five NOP instructions or more must be inserted immediately after setting the
IDLE1 mode, IDLE2 mode, or STOP mode (by setting the PSC.STP bit to 1).
p. 58
When a store instruction is executed to store data in the command register,
interrupts are not acknowledged. This is because it is assumed that steps <3>
and <4> above are performed by successive store instructions. If another
instruction is placed between <3> and <4>, and if an interrupt is acknowledged by
that instruction, the above sequence may not be established, causing malfunction.
p. 58
Setting data to
special
registers
Although dummy data is written to the PRCMD register, use the same general-
purpose register used to set the special register (<4> in Example) to write data to
the PRCMD register (<3> in Example). The same applies when a general-
purpose register is used for addressing.
p. 58
If 0 is written to the PRERR bit of the SYS register, which is not a special register,
immediately after a write access to the PRCMD register, the PRERR bit is cleared
to 0 (the write access takes precedence).
p. 60SYS register
If data is written to the PRCMD register, which is not a special register,
immediately after a write access to the PRCMD register, the PRERR bit is set to
1.
p. 60
Registers to be
set first
Be sure to set the following registers first when using the V850ES/JG3.
• System wait control register (VSWC)
• On-chip debug mode register (OCDM)
• Watchdog timer mode register 2 (WDTM2)
p. 61
VSWC register Three clocks are required to access an on-chip peripheral I/O register (without a
wait cycle). The V850ES/JG3 requires wait cycles according to the operating
frequency. Set the following value to the VSWC register in accordance with the
frequency used.
p. 61
Chapter 3
Soft
CPU
functions
Accessing
specific on-chip
peripheral I/O
registers
Accessing the above registers is prohibited in the following statuses. If a wait
cycle is generated, it can only be cleared by a reset.
• When the CPU operates with the subclock and the main clock oscillation is
stopped
• When the CPU operates with the internal oscillation clock
p. 62
Hard
Basic port
configuration
Ports 0, 3 to 5, and 9 are 5 V tolerant. p. 70
Soft
PFn register
The PFnm bit of the PFn register is valid only when the PMnm bit of the PMn
register is 0 (when the output mode is specified) in port mode (PMCnm bit = 0).
When the PMnm bit is 1 (when the input mode is specified), the set value of the
PFn register is invalid.
p. 68
Hard, soft
The DRST pin is used for on-chip debugging.
If on-chip debugging is not used, fix the P05/INTP2/DRST pin to low level
between when the reset signal of the RESET pin is released and when the
OCDM.OCDM0 bit is cleared (0).
For details, see 4.6.3 Cautions on on-chip debug pins.
p. 70
Hard
Port 0
The P02 to P06 pins have hysteresis characteristics in the input mode of the
alternate function, but do not have hysteresis characteristics in the port mode.
p. 70
PMC0 register The P05/INTP2/DRST pin becomes the DRST pin regardless of the value of the
PMC05 bit when the OCDM.OCDM0 bit = 1.
p. 71
PF0 register When an output pin is pulled up at EVDD or higher, be sure to set the PF0n bit to
1.
p. 72
P1 register Do not read or write the P1 register during D/A conversion (see 14.4.3 Cautions). p. 73
Chapter 4
Soft
Port
functions
PM1 register When using P1n as alternate functions (ANOn pin output), set the PM1n bit to 1. p. 73