Datasheet

V850ES/JG3 APPENDIX E LIST OF CAUTIONS
R01UH0015EJ0300 Rev.3.00 Page 834 of 870
Sep 30, 2010
APPENDIX E LIST OF CAUTIONS
This appendix lists cautions described in this document.
“Classification (hard/soft)” in table is as follows.
Hard: Cautions for microcontroller internal/external hardware
Soft: Cautions for software such as register settings or programs
(1/36)
Chapter
Classification
Function Details of
Function
Cautions Page
FLMD0 Connect these pins to VSS in the normal mode. p. 5
Chapter 1
Hard
Introduction
REGC Connect the REGC pin to V
SS via a 4.7 μ F (recommended value) capacitor. p. 5
Soft
P05 Incorporates a pull-down resistor. It can be disconnected by clearing the
OCDM.OCDM0 bit to 0.
p. 11
Hard
DDO In the on-chip debug mode, high-level output is forcibly set. p. 15
KR0 to KR7 Pull this pin up externally. p. 16
Soft
NMI The NMI pin alternately functions as the P02 pin. It functions as the P02 pin
after reset. To enable the NMI pin, set the PMC0.PMC02 bit to 1. The initial
setting of the NMI pin is “No edge detected”. Select the NMI pin valid edge
using INTF0 and INTR0 registers.
p. 16
Chapter 2
Hard
Pin
functions
When power is
turned on
When the power is turned on, the following pin may output an undefined level
temporarily, even during reset.
• P53/SIB2/KR3/TIQ00/TOQ00/RTP03/DDO pin
p. 24
EIPC register,
EIPSW register,
FEPC register,
FEPSW register
Because only one set of these registers is available, the contents of these
registers must be saved by program if multiple interrupts are enabled.
p. 28
EIPC, FEPC,
CTPC registers
Even if EIPC or FEPC, or bit 0 of CTPC is set to 1 by the LDSR instruction, bit 0
is ignored when execution is returned to the main routine by the RETI
instruction after interrupt servicing (this is because bit 0 of the PC is fixed to 0).
Set an even value to EIPC, FEPC, and CTPC (bit 0 = 0).
p. 28
Program space Because the 4 KB area of addresses 03FFF000H to 03FFFFFFH is an on-chip
peripheral I/O area, instructions cannot be fetched from this area. Therefore, do
not execute an operation in which the result of a branch address calculation
affects this area.
p. 36
When a register is accessed in word units, a word area is accessed twice in
halfword units in the order of lower area and higher area, with the lower 2 bits of
the address ignored.
p. 43
If a register that can be accessed in byte units is accessed in halfword units, the
higher 8 bits are undefined when the register is read, and data is written to the
lower 8 bits.
p. 43
On-chip
peripheral I/O
area
Addresses not defined as registers are reserved for future expansion. The
operation is undefined and not guaranteed when these addresses are
accessed.
p. 43
Chapter 3
Soft
CPU
functions
Internal RAM
area
If a branch instruction is at the upper limit of the internal RAM area, a prefetch
operation (invalid fetch) straddling the on-chip peripheral I/O area does not
occur.
p. 44