Datasheet

ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 100 32-Bit 32 MHz I/O number 84

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V850ES/JG3 APPENDIX D INSTRUCTION SET LIST

R01UH0015EJ0300 Rev.3.00 Page 831 of 870

Sep 30, 2010

(5/6)

Execution

Clock

Flags Mnemonic Operand Opcode Operation

i r l CY OV S Z SAT

bit#3,disp16[reg1] 00bbb111110RRRRR

dddddddddddddddd

adr←GR[reg1]+sign-extend(disp16)

Z flag←Not (Load-memory-bit(adr,bit#3))

Store-memory-bit(adr,bit#3,1)

Note 3

SET1

reg2,[reg1] rrrr r1 11 111 RR RR R

0000000011100000

adr←GR[reg1]

Z flag←Not(Load-memory-bit(adr,reg2))

Store-memory-bit(adr,reg2,1)

Note 3

reg1,reg2 rr rr r1 11111 RRRR R

0000000011000000

GR[reg2]←GR[reg2] logically shift left by GR[reg1] 1 1 1 × 0 × ×SHL

imm5,reg2 rrrrr010110iiiii

GR[reg2]←GR[reg2] logically shift left

by zero-extend(imm5)

11 1 × 0 × ×

reg1,reg2 rr rr r1 11111 RRRR R

0000000010000000

GR[reg2]←GR[reg2] logically shift right by GR[reg1] 1 1 1 × 0 × ×SHR

imm5,reg2 rrrrr010100iiiii

GR[reg2]←GR[reg2] logically shift right

by zero-extend(imm5)

11 1 × 0 × ×

SLD.B disp7[ep],reg2 r r r r r 0 1 1 0 d d d dd d d adr←ep+zero-extend(disp7)

GR[reg2]←sign-extend(Load-memory(adr,Byte))

Note 9

SLD.BU disp4[ep],reg2

rrrrr0000110dddd

Note 18

adr←ep+zero-extend(disp4)

GR[reg2]←zero-extend(Load-memory(adr,Byte))

Note 9

SLD.H disp8[ep],reg2 r r r r r 1 0 0 0 d d d d d d d

Note 19

adr←ep+zero-extend(disp8)

GR[reg2]←sign-extend(Load-memory(adr,Halfword))

Note 9

SLD.HU disp5[ep],reg2

rrrrr0000111dddd

Notes 18, 20

adr←ep+zero-extend(disp5)

GR[reg2]←zero-extend(Load-memory(adr,Halfword))

Note 9

SLD.W disp8[ep],reg2 rrrrr1010dddddd0

Note 21

adr←ep+zero-extend(disp8)

GR[reg2]←Load-memory(adr,Word)

Note 9

SST.B reg2,disp7[ep] r r r r r 0 1 1 1 d d d d d d d adr←ep+zero-extend(disp7)

Store-memory(adr,GR[reg2],Byte)

11 1

SST.H reg2,disp8[ep] r r r r r 1 0 0 1 d d d d d d d

Note 19

adr←ep+zero-extend(disp8)

Store-memory(adr,GR[reg2],Halfword)

11 1

SST.W reg2,disp8[ep] rrrrr1010dddddd1

Note 21

adr←ep+zero-extend(disp8)

Store-memory(adr,GR[reg2],Word)

11 1

ST.B reg2,disp16[reg1] rrrr r1 11 010 RRRR R

dddddddddddddddd

adr←GR[reg1]+sign-extend(disp16)

Store-memory(adr,GR[reg2],Byte)

11 1

ST.H reg2,disp16[reg1] rr rrr 111 01 1RRRRR

ddddddddddddddd0

Note 8

adr←GR[reg1]+sign-extend(disp16)

Store-memory (adr,GR[reg2], Halfword)

11 1

ST.W reg2,disp16[reg1] rrrrr111011RRRRR

ddddddddddddddd1

Note 8

adr←GR[reg1]+sign-extend(disp16)

Store-memory (adr,GR[reg2], Word)

11 1

STSR regID,reg2 rr rrr 111 11 1RRRRR

0000000001000000

GR[reg2]←SR[regID] 1 1 1