Datasheet

V850ES/JG3 APPENDIX D INSTRUCTION SET LIST
R01UH0015EJ0300 Rev.3.00 Page 828 of 870
Sep 30, 2010
(2/6)
Execution
Clock
Flags Mnemonic Operand Opcode Operation
i r l CY OV S Z SAT
DBTRAP 1111100001000000 DBPC←PC+2 (restored PC)
DBPSW←PSW
PSW.NP←1
PSW.EP←1
PSW.ID←1
PC←00000060H
33 3
DI 0000011111100000
0000000101100000
PSW.ID←1 1 1 1
imm5,list12 0000011001iiiiiL
LLLLLLLLLLL00000
sp←sp+zero-extend(imm5 logically shift left by 2)
GR[reg in list12]←Load-memory(sp,Word)
sp←sp+4
repeat 2 steps above until all regs in list12 is loaded
n+1
Note 4
n+1
Note 4
n+1
Note 4
DISPOSE
imm5,list12,[reg1] 0 0 0 0 0 1 1 0 0 1 i i i i i L
LLLLLLLLLLLRRRRR
Note 5
sp←sp+zero-extend(imm5 logically shift left by 2)
GR[reg in list12]←Load-memory(sp,Word)
sp←sp+4
repeat 2 steps above until all regs in list12 is loaded
PC←GR[reg1]
n+3
Note 4
n+3
Note 4
n+3
Note 4
DIV reg1,reg2,reg3 rr rr r11 11 11R RRRR
wwwww01011000000
GR[reg2]←GR[reg2]÷GR[reg1]
GR[reg3]←GR[reg2]%GR[reg1]
35 35 35 × × ×
reg1,reg2 rr rr r0 00010 RRRR R
GR[reg2]←GR[reg2]÷GR[reg1]
Note 6
35 35 35 × × ×
DIVH
reg1,reg2,reg3 rrr rr1 11 11 1RRRRR
wwwww01010000000
GR[reg2]←GR[reg2]÷GR[reg1]
Note 6
GR[reg3]←GR[reg2]%GR[reg1]
35 35 35 × × ×
DIVHU reg1,reg2,reg3 r r rr r11 11 11R RRRR
wwwww01010000010
GR[reg2]←GR[reg2]÷GR[reg1]
Note 6
GR[reg3]←GR[reg2]%GR[reg1]
34 34 34 × × ×
DIVU reg1,reg2,reg3 rr rr r1 11 111 RRRR R
wwwww01011000010
GR[reg2]←GR[reg2]÷GR[reg1]
GR[reg3]←GR[reg2]%GR[reg1]
34 34 34 × × ×
EI 1000011111100000
0000000101100000
PSW.ID←0 1 1 1
HALT 0000011111100000
0000000100100000
Stop 1 1 1
HSW reg2,reg3 r r r r r1 11 1 1 1 0 0 0 0 0
wwwww01101000100
GR[reg3]←GR[reg2](15 : 0) ll GR[reg2] (31 : 16) 1 1 1 × 0 × ×
JARL disp22,reg2 r r r r r 1 1 1 1 0 d d d d d d
ddddddddddddddd0
Note 7
GR[reg2]←PC+4
PC←PC+sign-extend(disp22)
22 2
JMP [reg1] 00000000011RRRRR PC←GR[reg1] 3 3 3
JR disp22 0000011110dddddd
ddddddddddddddd0
Note 7
PC←PC+sign-extend(disp22) 2 2 2
LD.B disp16[reg1],reg2 rrrr r1 11 000 RRRR R
dddddddddddddddd
adr←GR[reg1]+sign-extend(disp16)
GR[reg2]←sign-extend(Load-memory(adr,Byte))
11
Note
11
LD.BU disp16[reg1],reg2 rrr rr1 11 10 b RR RR R
dddddddddddddd1
Notes 8, 10
adr←GR[reg1]+sign-extend(disp16)
GR[reg2]←zero-extend(Load-memory(adr,Byte))
11
Note
11