Datasheet

ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 100 32-Bit 32 MHz I/O number 84

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V850ES/JG3 APPENDIX D INSTRUCTION SET LIST

R01UH0015EJ0300 Rev.3.00 Page 827 of 870

Sep 30, 2010

D.2 Instruction Set (in Alphabetical Order)

(1/6)

Execution

Clock

Flags Mnemonic Operand Opcode Operation

i r l CY OV S Z SAT

reg1,reg2 rr rr r0 01110 RRRR R GR[reg2]←GR[reg2]+GR[reg1] 1 1 1 × × × ×ADD

imm5,reg2 r r r r r 0 1 0 010iiiii GR[reg2]←GR[reg2]+sign-extend(imm5) 1 1 1 × × × ×

ADDI imm16,reg1,reg2 r r rr r1 100 00 R RRRR

iiiiiiiiiiiiiiii

GR[reg2]←GR[reg1]+sign-extend(imm16) 1 1 1 × × × ×

AND reg1,reg2 rr rrr 001 01 0RRRRR GR[reg2]←GR[reg2]AND GR[reg1] 1 1 1 0 × ×

ANDI imm16,reg1,reg2 r r rr r1 101 10 R RRRR

iiiiiiiiiiiiiiii

GR[reg2]←GR[reg1]AND zero-extend(imm16) 1 1 1 0 × ×

When conditions

are satisfied

Note 2

Bcond disp9 ddddd1011dddcccc

Note 1

if conditions are satisfied

then PC←PC+sign-extend(disp9)

When conditions

are not satisfied

11 1

BSH reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0

wwwww01101000010

GR[reg3]←GR[reg2] (23 : 16) ll GR[reg2] (31 : 24) ll

GR[reg2] (7 : 0) ll GR[reg2] (15 : 8)

11 1 × 0 × ×

BSW reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 00 0

wwwww01101000000

GR[reg3]←GR[reg2] (7 : 0) ll GR[reg2] (15 : 8) ll GR

[reg2] (23 : 16) ll GR[reg2] (31 : 24)

11 1 × 0 × ×

CALLT imm6 0000001000iiiiii CTPC←PC+2(return PC)

CTPSW←PSW

adr←CTBP+zero-extend(imm6 logically shift left by 1)

PC←CTBP+zero-extend(Load-memory(adr,Halfword))

44 4

bit#3,disp16[reg1] 10bbb111110RRRRR

dddddddddddddddd

adr←GR[reg1]+sign-extend(disp16)

Z flag←Not(Load-memory-bit(adr,bit#3))

Store-memory-bit(adr,bit#3,0)

Note 3

CLR1

reg2,[reg1] rrrr r1 11 111 RR RR R

0000000011100100

adr←GR[reg1]

Z flag←Not(Load-memory-bit(adr,reg2))

Store-memory-bit(adr,reg2,0)

Note 3

cccc,imm5,reg2,reg3 r r r r r 1 1 1 111iiiii

wwwww011000cccc0

if conditions are satisfied

then GR[reg3]←sign-extended(imm5)

else GR[reg3]←GR[reg2]

11 1 CMOV

cccc,reg1,reg2,reg3 r r r r r 1 1 1 1 1 1 RR RR

wwwww011001cccc0

if conditions are satisfied

then GR[reg3]←GR[reg1]

else GR[reg3]←GR[reg2]

11 1

reg1,reg2 rr rr r0 011 11 RRRR R result←GR[reg2]–GR[reg1] 1 1 1 × × × ×CMP

imm5,reg2 r r r r r 0 1 0 011iiiii result←GR[reg2]–sign-extend(imm5) 1 1 1 × × × ×

CTRET 0000011111100000

0000000101000100

PC←CTPC

PSW←CTPSW

3 3 3 R R R R R

DBRET 0000011111100000

0000000101000110

PC←DBPC

PSW←DBPSW

3 3 3 R R R R R