Datasheet

V850ES/JG3 APPENDIX B MAJOR DIFFERENCES BETWEEN V850ES/JG3 AND V850ES/JG2
R01UH0015EJ0300 Rev.3.00 Page 812 of 870
Sep 30, 2010
APPENDIX B MAJOR DIFFERENCES BETWEEN V850ES/JG3 AND V850ES/JG2
Differences between the V850ES/JG3 and V850ES/JG2 are shown below. For details, refer to each corresponding
section.
Table B-1. Major Differences Between V850ES/JG3 and V850ES/JG2 (1/2)
Major Differences V850ES/JG3 V850ES/JG2 Refer to:
BVDD, BVSS pins Changed to EVDD, EVSS pins Provided Throughout
Introduction: Minimum instruction
execution time
31.25 ns 50 ns 1.2
Pin function: Pin status of
P10/ANO0, P11/ANO1 (when
power is applied)
Hi-Z Undefined 2.2
Internal flash memory 384/512/768/1024 KB 128/256/384/512/640 KB 3.4.4 (1)
CPU
function
Internal RAM 32/40/60 KB 12/24/32/40/48 KB 3.4.4 (2)
A/D converter: Proportion of
sampling time during conversion
8/26 clocks 4/26 clocks 13.5.2
Reset function: Firmware operation
after releasing internal system
reset
None
Provided (refer to 22.3.4 (2) in Users
Manual (U17715E))
Low-voltage detection
interrupt (INTLVI)
occurrence source
When supply voltage drops or rises
across the detection voltage
When supply voltage drops below the
detection voltage
24.3 (1)
Low-voltage detection
level
2.85 to 3.05 V (2.95 V (TYP.))
2.85 to 3.15 V (3.0 V (TYP.))
24.3 (2)
Low-
voltage
detector
(LVI)
RAMS.RAMF bit set
conditions
Voltage lower than detection level is
detected
Set by instruction
Voltage lower than detection level is
detected
Set by instruction
Reset by WDT2 and CLM occurs
Reset by RESET pin occurs during
internal RAM accessing
24.3 (3)
CRC function Provided None Chapter 25
Regulator: Supply clock to sub-
oscillator
Supply voltage (V
DD) Regulator output voltage 26.1
Block configuration Block 0 to last block: 4 KB each
Blocks 0 to 3: 28 KB each
Blocks 4 to 7: 4 KB each
Block 8 to last block: 64 KB each
Flash
memory
Boot area 64 KB 56 KB
27.2
On-chip
debug
function
Cautions on reset
related to software
breakpoint
None
Provided (refer to 27.1.6 (3) in Users
Manual (U17715E))