Datasheet

V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS
R01UH0015EJ0300 Rev.3.00 Page 797 of 870
Sep 30, 2010
RAM Retention Detection
(TA = −40 to +85°C, VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = AVSS = 0 V, CL = 50 pF)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Detection voltage VRAMH 1.9 2.0 2.1 V
Supply voltage rise time tRAMHTH VDD = 0 to 2.85 V 0.002 ms
Response time
Note
tRAMHD After VDD reaches 2.1 V 0.2 3.0 ms
Minimum pulse width tRAMHW 0.2 ms
Note Time required to detect the detection voltage and set the RAMS.RAMF bit.
Supply voltage
(V
DD)
Time
Detection voltage (MIN.)
Operating voltage (MIN.)
Detection voltage (TYP.)
Detection voltage (MAX.)
tRAMHW
tRAMHDtRAMHD
tRAMHTH
RAMS.RAMF bit
Cleared by instruction