Datasheet

V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS
R01UH0015EJ0300 Rev.3.00 Page 794 of 870
Sep 30, 2010
I
2
C Bus Mode (TA = 40 to +85°C, VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = AVSS = 0 V, CL = 50 pF)
Normal Mode High-Speed Mode Parameter Symbol
MIN. MAX. MIN. MAX.
Unit
SCL0n clock frequency fCLK 0 100 0 400 kHz
Bus free time
(Between start and stop conditions)
t
BUF <99> 4.7
1.3
μ
s
Hold time
Note 1
tHD: STA <100> 4.0
0.6
μ
s
SCL0n clock low-level width tLOW <101> 4.7
1.3
μ
s
SCL0n clock high-level width tHIGH <102> 4.0
0.6
μ
s
Setup time for start/restart conditions tSU: STA <103> 4.7
0.6
μ
s
CBUS compatible
master
5.0
μ
s Data hold time
I
2
C mode
t
HD: DAT <104>
0
Note 2
0
Note 2
0.9
Note 3
μ
s
Data setup time tSU: DAT <105> 250
100
Note 4
ns
SDA0n and SCL0n signal rise time tR <106>
1000 20 + 0.1Cb
Note 5
300 ns
SDA0n and SCL0n signal fall time tF <107>
300 20 + 0.1Cb
Note 5
300 ns
Stop condition setup time tSU: STO <108> 4.0
0.6
μ
s
Pulse width of spike suppressed by
input filter
t
SP <109>
0 50 ns
Capacitance load of each bus line Cb
400
400 pF
Notes 1. At the start condition, the first clock pulse is generated after the hold time.
2. The system requires a minimum of 300 ns hold time internally for the SDA0n signal (at V
IHmin. of SCL0n signal)
in order to occupy the undefined area at the falling edge of SCL0n.
3. If the system does not extend the SCL0n signal low hold time (t
LOW), only the maximum data hold time
(t
HD:DAT) needs to be satisfied.
4. The high-speed mode I
2
C bus can be used in the normal-mode I
2
C bus system. In this case, set the
high-speed mode I
2
C bus so that it meets the following conditions.
If the system does not extend the SCL0n signal’s low state hold time:
t
SU:DAT 250 ns
If the system extends the SCL0n signal’s low state hold time:
Transmit the following data bit to the SDA0n line prior to the SCL0n line release (t
Rmax. + tSU:DAT = 1,000 +
250 = 1,250 ns: Normal mode I
2
C bus specification).
5. Cb: Total capacitance of one bus line (unit: pF)
Remark n = 0 to 2