Datasheet

V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS
R01UH0015EJ0300 Rev.3.00 Page 793 of 870
Sep 30, 2010
CSIB Timing
(1) Master mode
(T
A = −40 to +85°C, VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = AVSS = 0 V, CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
SCKBn cycle time tKCY1 <94> 125 ns
SCKBn high-/low-level width
t
KH1,
t
KL1
<95> t
KCY1/2 − 8 ns
SIBn setup time (to SCKBn↑) tSIK1 <96> 27 ns
SIBn hold time (from SCKBn↑) tKSI1 <97> 27 ns
Delay time from SCKBn↓ to SOBn output tKSO1 <98> 27 ns
Remark n = 0 to 4
(2) Slave mode
(T
A = −40 to +85°C, VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = AVSS = 0 V, CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
SCKBn cycle time tKCY2 <94> 125 ns
SCKBn high-/low-level width
t
KH2,
t
KL2
<95> 54.5 ns
SIBn setup time (to SCKBn↑) tSIK2 <96> 27 ns
SIBn hold time (from SCKBn↑) tKSI2 <97> 27 ns
Delay time from SCKBn↓ to SOBn output tKSO2 <98> 27 ns
Remark n = 0 to 4
SOBn (output)
Input data
Output data
SIBn (input)
SCKBn (I/O)
<94>
<95> <95>
<96> <97>
<98>
Hi-Z Hi-Z
Remark n = 0 to 4