Datasheet

V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS
R01UH0015EJ0300 Rev.3.00 Page 791 of 870
Sep 30, 2010
Power On/Power Off/Reset Timing
(TA = −40 to +85°C, VSS = AVSS = EVSS = 0 V, CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
EVDD↑ → VDD↑ tREL <87> 0 ns
EVDD↑ → AVREF0, AVREF1↑ tREA <88>
0 t
REL
ns
VDD↑ → RESET↑ tRER <89>
500 +
t
REG
Note
ns
Analog noise elimination (during flash erase/
writing)
500
ns
RESET low-level width tWRSL <90>
Analog noise elimination
500
ns
RESET↓ → VDD↓ tFRE <91>
500
ns
VDD↓ → EVDD↓ tFEL <92>
0
ns
AVREF0↓ → EVDD↓ tFEA <93>
0
tFEL ns
Note Depends on the on-chip regulator characteristics.
V DD
EV DD
V I V I V I V I
AV REF0
RESET (input)
<87>
<89>
<91><90>
<88>
<92>
<93>
Interrupt Timing
(T
A = −40 to +85°C, VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = AVSS = 0 V, CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
NMI high-level width tWNIH Analog noise elimination 500 ns
NMI low-level width tWNIL Analog noise elimination 500 ns
n = 0 to 7 (Analog noise elimination) 500 ns INTPn high-level width tWITH
n = 3 (Digital noise elimination) 3T
SMP + 20 ns
n = 0 to 7 (Analog noise elimination) 500 ns INTPn low-level width tWITL
n = 3 (Digital noise elimination) 3T
SMP + 20 ns
Remark T
SMP: Noise elimination sampling clock cycle