Datasheet

V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS
R01UH0015EJ0300 Rev.3.00 Page 790 of 870
Sep 30, 2010
(b) CLKOUT synchronous
(T
A = −40 to +85°C, VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = AVSS = 0 V, CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
HLDRQ setup time (to CLKOUT↓) tSHQK <83> 20 ns
HLDRQ hold time (from CLKOUT↓) tHKHQ <84> 5 ns
Delay time from CLKOUT↑ to bus float tDKF <85> 19 ns
Delay time from CLKOUT↑ to HLDAK tDKHA <86> 19 ns
Remark The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1.
Bus Hold (CLKOUT Synchronous)
CLKOUT (output)
HLDRQ (input)
HLDAK (output)
Address bus (output)
Data bus (I/O)
TH TH THT2 T3 TI TI
Hi-Z
ASTB (output)
RD (output),
WR0, WR1 (output)
Hi-Z
Hi-Z
<83>
<83>
<86><86>
<84>
<85>