Datasheet

V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS
R01UH0015EJ0300 Rev.3.00 Page 789 of 870
Sep 30, 2010
(3) Bus hold
(a) CLKOUT asynchronous
(T
A = −40 to +85°C, VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = AVSS = 0 V, CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
HLDRQ high-level width tWHQH <78> T + 10 ns
HLDAK low-level width tWHAL <79> T − 15 ns
Delay time from HLDAK↑ to bus output tDHAC <80> −3 ns
Delay time from HLDRQ↓ to HLDAK↓ tDHQHA1 <81> (2n + 7.5)T + 26 ns
Delay time from HLDRQ↑ to HLDAK↑ tDHQHA2 <82> 0.5T 1.5T + 26 ns
Remarks 1. T = 1/fCPU (fCPU: CPU operating clock frequency)
2. n: Number of wait clocks inserted in the bus cycle
The sampling timing changes when a programmable wait is inserted.
3. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1.
Bus Hold (CLKOUT Asynchronous)
CLKOUT (output)
HLDRQ (input)
HLDAK (output)
Address bus (output)
Data bus (I/O)
TH TH THTI TI
Hi-Z
ASTB (output)
RD (output),
WR0, WR1 (output)
Hi-Z
Hi-Z
<78>
<82>
<79>
<80>
<81>