Datasheet

V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS
R01UH0015EJ0300 Rev.3.00 Page 788 of 870
Sep 30, 2010
(d) Write cycle (CLKOUT synchronous): In separate bus mode
(T
A = −40 to +85°C, VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = AVSS = 0 V, CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
Delay time from CLKOUT↑ to address tDKSA <73> 0 27 ns
Delay time from CLKOUT↑ to data
output
t
DKSD <74> 0 18 ns
Delay time from CLKOUT↑↓ to WRm tDKSW <75> −2 12 ns
WAIT setup time (to CLKOUT↑) tSWTK <76> 20 ns
WAIT hold time (from CLKOUT↑) tHKWT <77> 0 ns
Remarks 1. m = 0, 1
2. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1.
Write Cycle (CLKOUT Synchronous): In Separate Bus Mode
CLKOUT (output)
T1
<74>
<75>
<77><76>
<75>
TW T2
WR0, WR1
(output)
A0 to A21 (output)
AD0 to AD15 (I/O)
WAIT (input)
<73> <73>
<77><76>
<74>
Hi-Z Hi-Z
Remark RD is high level.