Datasheet

V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS
R01UH0015EJ0300 Rev.3.00 Page 787 of 870
Sep 30, 2010
(c) Read cycle (CLKOUT synchronous): In separate bus mode
(T
A = −40 to +85°C, VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = AVSS = 0 V, CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
Delay time from CLKOUT↑ to address tDKSA <67> 0 27 ns
Data input setup time (to CLKOUT↑) tSISDK <68> 20 ns
Data input hold time (from CLKOUT↑) tHKISD <69> 0 ns
Delay time from CLKOUT↓↑ to RD tDKSR <70> −2 12 ns
WAIT setup time (to CLKOUT↑) tSWTK <71> 20 ns
WAIT hold time (from CLKOUT↑) tHKWT <72> 0 ns
Remark The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1.
Read Cycle (CLKOUT Synchronous, 1 Wait): In Separate Bus Mode
CLKOUT (output)
T1
<70>
<71>
<72>
<71> <72>
<67>
<70>
<68> <69>
Hi-ZHi-Z
TW T2
RD
(output)
A0 to A21 (output)
AD0 to AD15 (I/O)
WAIT (input)
<67>
Remark WR0 and WR1 are high level.