Datasheet

V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS
R01UH0015EJ0300 Rev.3.00 Page 785 of 870
Sep 30, 2010
(b) Write cycle (CLKOUT asynchronous): In separate bus mode
(T
A = −40 to +85°C, VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = AVSS = 0 V, CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
Address setup time (to WRm↓) tSAWR <52> (1 + tASW + tAHW)T − 27 ns
Address hold time (from WRm↑) tHAWR <53>
0.5T − 6
ns
WRm low-level width tWWRL <54> (0.5 + n)T − 10 ns
Data output time from WRm↓ tDOSDW <55> −5 ns
Data setup time (to WRm↑) tSOSDW <56> (0.5 + n)T − 20 ns
Data hold time (from WRm↑) tHOSDW <57> 0.5T − 7 ns
Data setup time (to address) tSAOD <58> (1 + tASW + tAHW)T − 25 ns
tSWRWT1 <59> 22 ns WAIT setup time (to WRm↓)
t
SWRWT2 <60> nT − 22 ns
tHWRWT1 <61> 0 ns WAIT hold time (from WRm↓)
t
HWRWT2 <62> nT ns
tSAWT1 <63> (1 + tASW + tAHW)T − 45 ns WAIT setup time (to address)
t
SAWT2 <64> (1 + n + tASW + tAHW)T − 45 ns
tHAWT1 <65> (n + tASW + tAHW)T ns WAIT hold time (from address)
t
HAWT2 <66> (1 + n + tASW + tAHW)T ns
Remarks 1. m = 0, 1
2. t
ASW: Number of address setup wait clocks
t
AHW: Number of address hold wait clocks
3. T = 1/f
CPU (fCPU: CPU operating clock frequency)
4. n: Number of wait clocks inserted in the bus cycle
The sampling timing changes when a programmable wait is inserted.
5. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1.