Datasheet

V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS
R01UH0015EJ0300 Rev.3.00 Page 783 of 870
Sep 30, 2010
(2) In separate bus mode
Caution When operating at f
XX > 20 MHz, be sure to insert address hold waits, address setup waits, and
data waits.
(a) Read cycle (CLKOUT asynchronous): In separate bus mode
(T
A = −40 to +85°C, VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = AVSS = 0 V, CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
Address setup time (to RD↓) tSARD <38> (0.5 + tASW)T − 27 ns
Address hold time (from RD↑) tHARD <39>
IT − 3.5
Note
ns
RD low-level width tWRDL <40> (1.5 + n + tAHW)T − 10 ns
Data setup time (to RD↑) tSISD <41> 23 ns
Data hold time (from RD↑) tHISD <42> −3.5 ns
Data setup time (to address) tSAID <43> (2 + n + tASW + tAHW)T − 40 ns
tSRDWT1 <44> (0.5 + tAHW)T − 25 ns WAIT setup time (to RD↓)
t
SRDWT2 <45> (0.5 + n + tAHW)T − 25 ns
tHRDWT1 <46> (n − 0.5 + tAHW)T ns WAIT hold time (from RD↓)
t
HRDWT2 <47> (n + 0.5 + tAHW)T ns
tSAWT1 <48> (1 + tASW + tAHW)T − 45 ns WAIT setup time (to address)
t
SAWT2 <49> (1 + n + tASW + tAHW)T − 45 ns
tHAWT1 <50> (n + tASW + tAHW)T ns WAIT hold time (from address)
t
HAWT2 <51> (1 + n + tASW + tAHW)T ns
Note The address may be changed during the low-level period of the RD pin. To avoid the address change, insert an
idle wait.
Remarks 1. t
ASW: Number of address setup wait clocks
t
AHW: Number of address hold wait clocks
2. T = 1/f
CPU (fCPU: CPU operating clock frequency)
3. n: Number of wait clocks inserted in the bus cycle
The sampling timing changes when a programmable wait is inserted
4. i: Number of idle states inserted after a read cycle (0 or 1)
5. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1.