Datasheet

V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS
R01UH0015EJ0300 Rev.3.00 Page 781 of 870
Sep 30, 2010
(b) Read/write cycle (CLKOUT synchronous): In multiplexed bus mode
(T
A = −40 to +85°C, VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = AVSS = 0 V, CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
Delay time from CLKOUT↑ to address tDKA <29> 0 25 ns
Delay time from CLKOUT↑ to address
float
tFKA <30> 0 19 ns
Delay time from CLKOUT↓ to ASTB tDKST <31> −12 7 ns
Delay time from CLKOUT↑ to RD, WRm tDKRDWR <32> −5 14 ns
Data input setup time (to CLKOUT↑) tSIDK <33> 15 ns
Data input hold time (from CLKOUT↑) tHKID <34> 5 ns
Data output delay time from CLKOUT↑ tDKOD <35> 19 ns
WAIT setup time (to CLKOUT↓) tSWTK <36> 20 ns
WAIT hold time (from CLKOUT↓) tHKWT <37> 5 ns
Remarks 1. m = 0, 1
2. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1.
Read Cycle (CLKOUT Synchronous): In Multiplexed Bus Mode
CLKOUT (output)
AD0 to AD15 (I/O)
A16 to A21 (output)
ASTB (output)
RD (output)
WAIT (input)
T1 T2 TW T3
DataAddress
Hi-Z
<29>
<31>
<32>
<30>
<31>
<32>
<36>
<36>
<37>
<37>
<33> <34>
Remark WR0 and WR1 are high level.