Datasheet

V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS
R01UH0015EJ0300 Rev.3.00 Page 778 of 870
Sep 30, 2010
Bus Timing
(1) In multiplexed bus mode
Caution When operating at f
XX > 20 MHz, be sure to insert address hold waits and address setup waits.
(a) Read/write cycle (CLKOUT asynchronous)
(T
A = −40 to +85°C, VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = AVSS = 0 V, CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
Address setup time (to ASTB↓) tSAST <6> (0.5 + tASW)T − 20 ns
Address hold time (from ASTB↓) tHSTA <7> (0.5 + tAHW)T − 15 ns
Delay time from RD↓ to address float tFRDA <8> 16 ns
Data input setup time from address tSAID <9> (2 + n + t ASW + t AHW )T − 35 ns
Data input setup time from RD↓ tSRID <10> (1 + n)T − 25 ns
Delay time from ASTB↓ to RD, WRm↓ tDSTRDWR <11> (0.5 + tAHW)T − 15 ns
Data input hold time (from RD↑) tHRDID <12> 0 ns
Address output time from RD↑ tDRDA <13> (1 + i)T − 15 ns
Delay time from RD, WRm↑ to ASTB↑ tDRDWRST <14> 0.5T − 15 ns
Delay time from RD↑ to ASTB↓ tDRDST <15> (1.5 + i + t ASW )T − 15 ns
RD, WRm low-level width tWRDWRL <16> (1 + n)T − 15 ns
ASTB high-level width tWSTH <17> (1 + i + tASW)T − 15 ns
Data output time from WRm↓ tDWROD <18> 15 ns
Data output setup time (to WRm↑) tSODWR <19> (1 + n)T − 20 ns
Data output hold time (from WRm↑) tHWROD <20> T − 15 ns
tSAWT1 <21> n ≥ 1 (1.5 + t ASW + t AHW )T − 35 ns WAIT setup time (to address)
t
SAWT2 <22> (1.5 + n + t ASW + t AHW )T − 35 ns
tHAWT1 <23> n ≥ 1 (0.5 + n + t ASW + t AHW )T ns WAIT hold time (from address)
t
HAWT2 <24> (1.5 + n + t ASW + t AHW )T ns
tSSTWT1 <25> n ≥ 1 (1 + tAHW)T − 25 ns WAIT setup time (to ASTB↓)
t
SSTWT2 <26> (1 + n + tAHW)T − 25 ns
tHSTWT1 <27> n ≥ 1 (n + tAHW)T ns WAIT hold time (from ASTB↓)
t
HSTWT2 <28> (1 + n + tAHW)T ns
Remarks 1. t
ASW: Number of address setup wait clocks
t
AHW: Number of address hold wait clocks
2. T = 1/f
CPU (fCPU: CPU operating clock frequency)
3. n: Number of wait clocks inserted in the bus cycle
The sampling timing changes when a programmable wait is inserted.
4. m = 0, 1
5. i: Number of idle states inserted after a read cycle (0 or 1)
6. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1.