Datasheet

V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS
R01UH0015EJ0300 Rev.3.00 Page 771 of 870
Sep 30, 2010
PLL Characteristics
(TA = −40 to +85°C, VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
×4 mode 2.5 5 MHz Input frequency fX
×8 mode 2.5 4 MHz
×4 mode 10 20 MHz Output frequency fXX
×8 mode 20 32 MHz
Lock time tPLL After VDD reaches 2.85 V (MIN.) 800 μ s
Internal Oscillator Characteristics
(T
A = −40 to +85°C, VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Output frequency fR 100 220 400 kHz
Regulator Characteristics
(T
A = −40 to +85°C, VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input voltage VDD fXX = 32 MHz (MAX.) 2.85 3.6 V
Output voltage VRO 2.5 V
Regulator output
stabilization time
t
REG
After V
DD reaches 2.85 V (MIN.),
Stabilization capacitance C = 4.7
μ F
(recommended value) connected to REGC
pin
1 ms
VDD
VRO
tREG
RESET